GLS85LD0512-60-RI-LBTE (Rev AC0) Greenliant, GLS85LD0512-60-RI-LBTE (Rev AC0) Datasheet - Page 4

• Manufacturer Part Number: GLS85LD0512-60-RI-LBTE (Rev AC0)
• Description: Memory Controllers 512MB NAND 60ns 3.3V Industrial
• Manufacturer: Greenliant

Specifications of GLS85LD0512-60-RI-LBTE (Rev AC0)

• Rohs: yes
• Battery Backup Switching: No
• Description/function: High-performance, fully-integrated, embedded flash solid-state drive
• Lithium Battery Monitor: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Current: 85 mA

Table 3-1: Pin Assignments (1 of 2)
These specifications are subject to change without notice.
© 2012 Greenliant Systems
GLS85LD1001T / GLS85LD512
Industrial Grade PATA NANDrive™
Host Side Interface
DMACK#
DMARQ
CS1FX#
CS3FX#
Symbol
IOWR#
IORD#
CSEL
D15
D14
D13
D12
D11
D10
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Pin No.
91-Ball
K8
K3
H8
G9
G8
H7
E8
H4
E3
H3
G3
G2
K2
H2
H9
L2
F9
F8
F7
F4
F3
F2
L3
L8
L9
J3
Type
Pin
I/O
O
I
I
I
I
I
I
I/O Type
I1Z/O2
I2U
I1U
I1Z
I2Z
I2Z
I2Z
O1
A[2:0] are used to select one of eight registers in the Task File.
D[15:0] Data bus
DMA Acknowledge - input from Host
DMA Request to Host
CS1FX# is the chip select for the task file registers
CS3FX# is used to select the alternate status register and the Device
Control register.
This internally pulled-up signal is used to configure this device as a
Master or a Slave. When this pin is grounded, this device is
configured as a Master. When the pin is open, this device is
configured as a Slave. The pin setting should remain the same from
Power-on to Power-down.
IORD#: This is an I/O Read Strobe generated by the Host. When
Ultra DMA mode is not active, this signal gates I/O data from the
device. (This pin supports three functions)
HDMARDY#: In Ultra DMA mode when DMA Read is active, this
signal is asserted by the Host to indicate that the Host is ready to
receive Ultra DMA data-in bursts. The Host may negate HDMARDY#
to pause an Ultra DMA transfer.
HSTROBE: When DMA Write is active, this signal is the data-out
strobe generated by the Host. Both the rising and falling edges of
HSTROBE cause data to be latched by the device. The Host may
stop generating HSTROBE edges to pause an Ultra DMA data-out
burst.
IOWR#: This is an I/O Write Strobe generated by the Host. When
Ultra DMA mode is not active, this signal is used to clock I/O data into
the device. (This pin supports two functions)
STOP: When Ultra DMA mode protocol is active, the assertion of this
signal causes the termination of the Ultra DMA burst
4
Name and Functions
Fact Sheet 01.000
October 2012
10/30/2012
S71382-F