CP2403-GMR Silicon Labs, CP2403-GMR Datasheet - Page 61

• Manufacturer Part Number: CP2403-GMR
• Description: LCD Drivers 64 Segment LCD driver I2C i/f
• Manufacturer: Silicon Labs

Specifications of CP2403-GMR

• Rohs: yes

10.1. Port I/O Modes of Operation
All port pins use the Port I/O cell shown in Figure 10.2. Each Port I/O cell can be configured by software for analog
I/O or digital I/O using the PnMDI registers. On reset or wake-up from ULP mode, all Port I/O cells default to a
digital high impedance state with weak pull-ups enabled.
10.1.1. Port Pins Configured for Analog I/O
Any pins to be used for LCD should be configured for analog I/O (PnMDI.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital output driver and receiver are disabled. Port pins configured for analog I/O
will always read back a value of 0 regardless of the actual voltage on the pin.
10.1.2. Port Pins Configured For Digital I/O
Any pins to be used for GPIO or Port Match should be configured as digital I/O (PnMDI.n = 1). For digital I/O pins,
one of two output modes (push-pull or open-drain) must be selected using the PnMDO registers.
Push-pull outputs (PnMDO.n = 1) always drive the Port pad to the V
logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the Port
pad to GND when the output logic value is 0 and become high impedance inputs (both high and low drivers turned
off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to the VDD
supply voltage to ensure the digital input is at a defined logic state. Weak pullups are disabled when the I/O cell is
driven to GND to minimize power consumption. The user must ensure that digital I/O are always internally or
externally pulled or driven to a valid logic state. An analog signal applied to a digital I/O pin will result in increased
power consumption.
PxOUT.x – Output
Logic Value
(Port Latch)
PxMDO.x
(1 for push-pull)
(0 for open-drain)
PxIN.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
PxMDI.x
(1 for digital)
(0 for analog)
Figure 10.2. Port I/O Cell Block Diagram
Rev. 1.0
DD
VDD
GND
or GND supply rails based on the output
VDD
CP2400/1/2/3
(WEAK)
PORT
PAD
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