AT28C64B-15PU Atmel, AT28C64B-15PU Datasheet - Page 4

• Manufacturer Part Number: AT28C64B-15PU
• Description: IC EEPROM 64KBIT 150NS 28DIP
• Manufacturer: Atmel

Specifications of AT28C64B-15PU

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Organization: 8 K x 8
• Interface Type: Parallel
• Access Time: 150 ns
• Output Enable Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 40 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Capacitance, Input: 4 pF
• Capacitance, Output: 8 pF
• Current, Input, Leakage: 10 μA
• Current, Operating: 40 mA
• Current, Output, Leakage: 10
• Data Retention: 10 yrs.
• Density: 64K
• Package Type: PDIP
• Power Dissipation: 220 mW
• Temperature, Operating: -40 to +85 °C
• Time, Access: 150 ns
• Time, Address Hold: 50
• Voltage, Input, High: 2 V
• Voltage, Input, Low: 0.8 V
• Voltage, Output, High: 2.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 5 V
• Memory Configuration: 8K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 28
• Rohs Compliant: Yes
• Operating Temperature Range: -40°C
• Ic Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4
4.5
4.6
4.6.1
4.6.2
4.7
4
DATA Polling
Toggle Bit
Data Protection
Device Identification
AT28C64B
Hardware Data Protection
Software Data Protection
The AT28C64B features DATA Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write
cycle.
In addition to DATA Polling, the AT28C64B provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle.
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28C64B in the following ways: (a)
V
– once V
ing a write; (c) write inhibit – holding any one of OE low, CE high, or WE high inhibits write
cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not ini-
tiate a write cycle.
A software controlled data protection feature has been implemented on the AT28C64B. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C64B is shipped from Atmel with SDP dis-
abled.
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (see “Software Data Protection Algorithms”
on
will be protected against inadvertent writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the AT28C64B by preceding the data to be writ-
ten by the same 3-byte command sequence used to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28C64B during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not actually written into the device; their
addresses may still be written with user data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device. However, for the duration of
t
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ±0.5V and using address locations 1FC0H to 1FFFH, the additional bytes may be
written to or read from in the same manner as the regular memory array.
WC
CC
page
, read operations will effectively be polling operations.
sense – if V
CC
10). After writing the 3-byte command sequence and waiting t
has reached 3.8 V, the device will automatically time out 5 ms (typical) before allow-
CC
is below 3.8 V (typical), the write function is inhibited; (b) V
®
has incorporated both hardware and software features that will protect the
WC
, the entire AT28C64B
CC
power-on delay
0270L–PEEPR–2/09