71V3558S200PFG

Manufacturer Part Number71V3558S200PFG
DescriptionSRAM
ManufacturerIDT
71V3558S200PFG datasheet
 


Specifications of 71V3558S200PFG

Product CategorySRAMRohsyes
Part # AliasesIDT71V3558S200PFG  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Page 1/28

Download datasheet (641Kb)Embed
Next
Features
◆ ◆ ◆ ◆ ◆
128K x 36, 256K x 18 memory configurations
◆ ◆ ◆ ◆ ◆
Supports high performance system speed - 200 MHz (x18)
(3.2 ns Clock-to-Data Access)
◆ ◆ ◆ ◆ ◆
Supports high performance system speed - 166 MHz (x36)
(3.5 ns Clock-to-Data Access)
◆ ◆ ◆ ◆ ◆
TM
ZBT
Feature - No dead cycles between write and read
cycles
◆ ◆ ◆ ◆ ◆
Internally synchronized output buffer enable eliminates the
need to control OE
◆ ◆ ◆ ◆ ◆
Single R/W (READ/WRITE) control pin
◆ ◆ ◆ ◆ ◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆ ◆ ◆ ◆ ◆
4-word burst capability (interleaved or linear)
◆ ◆ ◆ ◆ ◆
Individual byte write (BW
- BW
) control (May tie active)
1
4
◆ ◆ ◆ ◆ ◆
Three chip enables for simple depth expansion
◆ ◆ ◆ ◆ ◆
3.3V power supply (±5%), 3.3V I/O Supply (V
◆ ◆ ◆ ◆ ◆
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆ ◆ ◆ ◆ ◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Pin Description Summary
A
-A
Address Inputs
0
17
Chip Enables
, CE
, CE
CE
1
2
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
, BW
, BW
, BW
BW
1
2
3
4
CLK
Clock
ADV/LD
Advance b urst address / Load new address
Linear / Interleaved Burst Order
LBO
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
JTAG Reset (Optional)
TRST
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be
it read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be
used to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
DDQ)
user to deselect the device when desired. If any one of these three are
not asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
1
IDT71V3556S/XS
IDT71V3558S/XS
IDT71V3556SA/XSA
IDT71V3558SA/XSA
, or
TM
, CE
, CE
) that allow the
1
2
2
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5281 tbl 01
OCTOBER 2010
DSC-5281/11