71V3558S200PFG

Manufacturer Part Number71V3558S200PFG
DescriptionSRAM
ManufacturerIDT
71V3558S200PFG datasheet
 


Specifications of 71V3558S200PFG

Product CategorySRAMRohsyes
Part # AliasesIDT71V3558S200PFG  
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IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
JTAG Interface Specification (SA Version only)
t
JF
t
TCK
(1)
Device Inputs
/
TDI/TMS
(2)
Device Outputs
/
TDO
( 3)
TRST
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
(1,2,3,4)
Characteristics
Symbol
Parameter
t
JTAG Clock Input Period
JCYC
t
JTAG Clock HIGH
JCH
t
JTAG Clock Low
JCL
t
JTAG Clock Rise Time
JR
t
JTAG Clock Fall Time
JF
t
JTAG Reset
JRST
t
JTAG Reset Recovery
J RSR
t
JTAG Data Output
JCD
t
JTAG Data Output Hold
JDC
t
JTAG Setup
JS
t
JTAG Hold
JH
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
t
JCYC
t
JR
t
JCL
JCH
t
t
JS
JH
t
JRSR
Min.
Max.
Units
Scan Register Sizes
100
ns
____
40
ns
____
Instruction (IR)
40
ns
____
Bypass (BYR)
(1)
5
ns
____
JTAG Identification (JIDR)
(1)
5
ns
____
Boundary Scan (BSR)
50
____
ns
50
____
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
20
ns
____
by contacting your local IDT sales representative.
0
____
ns
25
ns
____
25
ns
____
I5281 tbl 01
22
6.42
Commercial and Industrial Temperature Ranges
t
JDC
t
JCD
M5281 drw 01
Register Name
Bit Size
4
1
32
Note (1)
x
I5281 tbl 03