IS62WV2568BLL-55TLI ISSI, Integrated Silicon Solution Inc, IS62WV2568BLL-55TLI Datasheet

IC SRAM 2MBIT 55NS 32TSOP

IS62WV2568BLL-55TLI

Manufacturer Part Number
IS62WV2568BLL-55TLI
Description
IC SRAM 2MBIT 55NS 32TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet

Specifications of IS62WV2568BLL-55TLI

Memory Size
2M (256K x 8)
Package / Case
32-TSOP
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
55ns
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
55 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
15 mA
Organization
256 K x 8
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
2.5 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1112
IS62WV2568BLL-55TLI

Available stocks

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Price
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IS62WV2568BLL-55TLI
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ISSI
Quantity:
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IS62WV2568BLL-55TLI
Manufacturer:
ISSI
Quantity:
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IS62WV2568BLL-55TLI
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IS62WV2568ALL
IS62WV2568BLL
256K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns, 55ns, 70ns
• CMOS low power operation
• TTL compatible interface levels
• Single power supply
• Fully static operation: no clock or refresh
• Three state outputs
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. H
1/6/10
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
– 1.65V--2.2V V
– 2.5V--3.6V V
required
cc
cc
(62WV2568BLL)
(62WV2568ALL)
I/O0-I/O7
A0-A17
VCC
GND
CS2
CS1
WE
OE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
1-800-379-4774
DESCRIPTION
The
speed, 2M bit static RAMs organized as 256K words
by 8 bits. It is fabricated using
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) , the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV2568ALL and IS62WV2568BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP
(TYPE I), and 36-pin mini BGA.
ISSI
MEMORY ARRAY
IS62WV2568ALL / IS62WV2568BLL are high-
COLUMN I/O
256K x 8
ISSI
JANUARY 2010
's high-performance
1

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IS62WV2568BLL-55TLI Summary of contents

Page 1

... Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV2568ALL and IS62WV2568BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP (TYPE I), and 36-pin mini BGA. ...

Page 2

... IS62WV2568ALL, IS62WV2568BLL PIN DESCRIPTIONS A0-A17 Address Inputs CS1 Chip Enable 1 Input CS2 Chip Enable 2 Input Output Enable Input OE Write Enable Input WE I/O0-I/O7Input/Output NC No Connection Vcc Power GND Ground PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm CS2 I/ I/ GND E Vcc F I/O6 NC A17 ...

Page 3

... IS62WV2568ALL, IS62WV2568BLL ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND term t Storage Temperature stg P Power Dissipation t Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 4

... IS62WV2568ALL, IS62WV2568BLL CAPACITANCE (1) Symbol Parameter c Input Capacitance In c Input/Output Capacitance out Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 1 ...

Page 5

... IS62WV2568ALL, IS62WV2568BLL POWER SUPPLY CHARACTERISTICS 62WV2568ALL (1.65V - 2.2V) Symbol Parameter Test Conditions I Vcc Dynamic Operating V cc Supply Current I out I Operating Supply Current I out I TTL Standby Current (TTL Inputs) V CS1 = CMOS Standby CS1 ≥ V Current (CMOS Inputs) CS2 ≤ 0.2V Note address and data inputs are cycling at the maximum frequency means no input lines change. ...

Page 6

... IS62WV2568ALL, IS62WV2568BLL READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time rc t Address Access Time AA t Output Hold Time ohA t /t CS1/CS2 Access Time 1 2 Acs Acs t OE Access Time doe t ( High-Z Output hzoe Low-Z Output (2) Lzoe t /t (2) CS1/CS2 to High-Z Output ...

Page 7

... IS62WV2568ALL, IS62WV2568BLL AC WAVEFORMS READ CYCLE NO. 2 (1,3) (CS1, CS2, OE Controlled) ADDRESS OE CS1 t ACS1/ CS2 DOUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1 Address is valid prior to or coincident with CS1 LOW and cs2 hIgh transition. Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 8

... IS62WV2568ALL, IS62WV2568BLL WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Wc t /tscs CS1/CS2 to Write End 1 2 scs t Address Setup Time to Write End AW t Address Hold from Write End hA t Addrress Setup Time Pulse Width PWe t Data Setup to Write End sd t Data Hold from Write End ...

Page 9

... IS62WV2568ALL, IS62WV2568BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CS1 CS2 DOUT DATA UNDEFINED DIN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE CS1 CS2 WE t DOUT DATA UNDEFINED DIN Integrated Silicon Solution, Inc. — www.issi.com Rev. H ...

Page 10

... IS62WV2568ALL, IS62WV2568BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V Vcc for Data Retention dr I Data Retention Current dr t Data Retention Setup Time sdr t Recovery Time rdr DATA RETENTION WAVEFORM (CS1 Controlled) t SDR V CC 3.0V 2. CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled 3.0 CS2 2 ...

Page 11

... Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 70 IS62WV2568BLL-70T 70 IS62WV2568BLL-70B 70 IS62WV2568BLL-70H Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 45 IS62WV2568BLL-45HLI 45 IS62WV2568BLL-45TLI 55 IS62WV2568BLL-55TI 55 IS62WV2568BLL-55TLI 55 IS62WV2568BLL-55BI 55 IS62WV2568BLL-55BLI 55 IS62WV2568BLL-55HI 55 IS62WV2568BLL-55HLI 70 IS62WV2568BLL-70TI 70 IS62WV2568BLL-70BI 70 IS62WV2568BLL-70HI Integrated Silicon Solution, Inc. — www.issi.com Rev. H 1/6/10 Package ...

Page 12

... IS62WV2568ALL, IS62WV2568BLL 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. H 1/6/10 ...

Page 13

... IS62WV2568ALL, IS62WV2568BLL Integrated Silicon Solution, Inc. — www.issi.com Rev. H 1/6/10 13 ...

Page 14

... IS62WV2568ALL, IS62WV2568BLL 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. H 1/6/10 ...

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