MT45W2MW16PGA-70 IT TR Micron Technology Inc, MT45W2MW16PGA-70 IT TR Datasheet
MT45W2MW16PGA-70 IT TR
Specifications of MT45W2MW16PGA-70 IT TR
Related parts for MT45W2MW16PGA-70 IT TR
MT45W2MW16PGA-70 IT TR Summary of contents
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... DQ11 A17 A7 DQ3 Vcc VccQ DQ12 NC A16 DQ4 Vss A15 DQ14 DQ13 A14 DQ5 DQ6 A13 DQ15 A19 A12 WE# DQ7 A18 A8 A9 A10 A11 A20 Top View (Ball Down) Part Number Example: MT45W2MW16PGA-70WT ©2007 Micron Technology, Inc. All rights reserved. Features ...
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... Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Timing Diagrams .22 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24zTOC.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2007 Micron Technology, Inc. All rights reserved. ...
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... Figure 22: WRITE Cycle (CE# Control .24 Figure 23: WRITE Cycle (LB#/UB# Control .25 Figure 24: 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24zLOF.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 IH Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2007 Micron Technology, Inc. All rights reserved. ...
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... Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 13: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24zLOT.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2007 Micron Technology, Inc. All rights reserved. ...
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... For seamless operation on an asynchronous memory bus, CellularRAM products incor- porate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Special attention has been focused on current consumption during self refresh. Cellu- larRAM products include three system-accessible mechanisms to minimize refresh current ...
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... Supply SS PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Description Address inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. ...
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... The device will consume active power in this mode whenever addresses are changed standby current. 6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Power CE# WE# Standby H X ...
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... The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, “Product Mark/Label,” at www.micron.com/csn. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory -70 Package Codes GA = VFBGA “ ...
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... SRAM products, popular in low-power, portable applications. The MT45W2MW16P contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. ...
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... LB#/UB# Figure 6: WRITE Operation CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Valid address Valid data READ cycle time Don’t Care t < CEM Valid address Valid data WRITE cycle time Don’ ...
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... During READ operations, enabled bytes are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ opera- tion. During WRITE operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first ...
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... Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. Data stored in addresses not receiving refresh will become corrupted ...
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... Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using CR software access. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Powe r-Up To enable PAR, bring ZZ# LOW for 10µs. ...
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... CR. The use of the software sequence does not affect the ability to perform the standard (ZZ#-controlled) method of loading the CR. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Valid address t < 500ns Q if the system will use DPD; DPD cannot be enabled or disabled using the CC Micron Technology, Inc ...
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... WE# LB#/UB# DATA Figure 11: Software Access Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Configuration Register Operation READ READ WRITE Address Address Address (MAX) (MAX) (MAX) XXXXh XXXXh 0000h ...
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... Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh The PAR bits restrict REFRESH operation to a portion of the total memory array. This feature allows the system to reduce current by only refreshing that part of the memory array required by the host system. The refresh options are full array, one-half array, one- quarter array, one-eighth array, or none of the array ...
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... Soldering temperature and time 10 seconds (solder ball only) Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Active Section Address Space Full die 000000h–1FFFFFh One-half of die 000000h– ...
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... Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W2MW16PGA device. The typical values shown in Figure 13 on page 19 are measured with the default on-chip temperature sensor control enabled. Table 6: ...
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... AC test inputs are driven at V times (10 percent to 90 percent) < 1.6ns. 2. Input timing begins at V the input test point may not be shown to scale. 3. Output timing ends at V PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Temperature (°C) Conditions 0V; +25°C IN ...
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... Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 20. The High-Z timings measure a 100mV transition from either V 3. Page mode enabled only. PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Test Point 50Ω VccQ/2 30pF ...
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... Write pulse width Write recovery time ZZ# LOW to WE# LOW Table 12: Deep Power-Down Timing Requirements Description Chip deselect to ZZ# LOW Deep power-down recovery Minimum ZZ# pulse width PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory Symbol Min ...
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... Initialization period (required before normal operations) Figure 17: Load Configuration Register ADDRESS CE# LB#/UB# WE# OE# ZZ# Figure 18: Deep Power-Down Entry and Exit ZZ# CE# PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory t PU Symbol OPCODE CDZZ t ZZWE t CDZZ t ZZ (MIN) ...
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... Figure 19: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Figure 20: Page Mode READ Operation (WE ADDRESS A[20:4] ADDRESS A[3:0] LB#/UB# DATA-OUT PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory ) Valid address BLZ t OE OE# t OLZ High-Z Don’t Care ...
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... Figure 21: WRITE Cycle (WE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT Figure 22: WRITE Cycle (CE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory t WC Valid address CE OE# t WHZ t WC Valid address CE OE WHZ 24 Timing Diagrams ...
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... Figure 23: WRITE Cycle (LB#/UB# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef82832fa7 / Source: 09005aef82832f97 32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN 32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory t WC Valid address CE OE WHZ 25 Timing Diagrams Valid data High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W2MW16PGA uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc ...