IS42S16400F-6TL ISSI, Integrated Silicon Solution Inc, IS42S16400F-6TL Datasheet - Page 6

• Manufacturer Part Number: IS42S16400F-6TL
• Description: IC SDRAM 64MBIT 166MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400F-6TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1075; IS42S16400F-6TL

IS42S16400F
IS45S16400F
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A7 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
being accessed will be precharged at the end of the READ
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determines
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
bank(s) is executed after passage of the period t
is the period required for bank precharging. Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 can be used
to enable the AUTO PRECHARGE function in conjunc-
tion with a specific READ or WRITE command. For each
individual READ or WRITE command, auto precharge is
6
command. When the auto precharge is selected, the row
burst. The row will remain open for subsequent accesses
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
will be ignored, and a WRITE will not be executed to that
byte/column location.
RP
, which
either enabled or disabled. AUTO PRECHARGE does not
apply except in full-page burst mode. Upon completion of
the READ or WRITE burst, a precharge of the bank/row
that is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(t
required for a single refresh operation, and no other com-
mands can be executed during this period. This command
is executed at least 4096 times every T
REFRESH command, address bits are “Don’t Care”. This
command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are gen-
erated automatically internally. SELF REFRESH can be
used to retain data in the SDRAM without external clocking,
even if the rest of the system is powered down. The SELF
REFRESH operation is started by dropping the CKE pin
from HIGH to LOW. During the SELF REFRESH operation
all other inputs to the SDRAM become “Don’t Care”. The
device must remain in self refresh mode for a minimum
period equal to t
for an indefinite period beyond that.The SELF-REFRESH
operation continues as long as the CKE pin remains LOW
and there is no need for external control of any other pins.
The next command cannot be executed until the device
internal recovery period (t
goes HIGH, the NOP command must be issued (minimum
of two clocks) to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
be refreshed, an AUTO-REFRESH should immediately be
performed for all addresses.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
Integrated Silicon Solution, Inc. — www.issi.com
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