M25P10-AVMP6TG NUMONYX, M25P10-AVMP6TG Datasheet - Page 30

• Manufacturer Part Number: M25P10-AVMP6TG
• Description: IC FLASH 1MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P10-AVMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P10-AVMP6TG; M25P10-AVMP6TGTR

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Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all write, program and erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, to reduce the standby current (from I
in
To take the device out of Deep Power-down mode, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The Release from Deep Power-down, and Read Electronic Signature (RES) instruction and
the Read Identification (RDID) instruction also allow the electronic signature of the device to
be output on Serial Data output (Q).
The Deep Power-down mode automatically stops at power-down, and the device always
powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t
to I
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
Table
S
C
D
CC2
and the Deep Power-down mode is entered.
14).
0
1
2
Instruction
3
4
5
6
Figure
7
17.
DP
t
Standby mode
DP
before the supply current is reduced
CC1
Deep Power-down mode
to I
CC2
, as specified
AI03753D