AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 71

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

12. I/O Ports
12.1
3714A–MICRO–711
Port Configuration
The AT89LP51RD2/ED2/ID2 can be configured for between 36 and 40 I/O pins. The exact num-
ber of general I/O pins available depends on the clock and external memory configuration as
shown in
Table 12-1.
Note:
All port pins on the AT89LP51RD2/ED2/ID2 may be configured in one of four modes: quasi-bidi-
rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port
modes may be assigned in software on a pin-by-pin basis as shown in
isters listed in
determines the default state of the port pins. When the fuse is enabled, all port pins on P1, P2
and P3 default to input-only mode after reset. When the fuse is disabled, all port pins on P1, P2
and P3 default to quasi-bidirectional mode after reset and are weakly pulled high. P0 always
defaults to open-drain mode. P4.4–5 always default to quasi-bidirectional mode. P4.0–1 always
default to open-drain. The other pins of P4 obey the fuse.
Each port pin also has a Schmitt-triggered input for improved input noise rejection. During
Power-down all the Schmitt-triggered inputs are disabled with the exception of P3.2 (INT0), P3.3
(INT1), RST, P4.6 (XTAL1) and P4.7 (XTAL2). Therefore, P3.2, P3.3, P4.6 and P4.7 should not
be left floating during Power-down. n addition any pin of Port 1 configured as a keyboard inter-
rupt input will also remain active during Power-down to wake-up the device. These interrupt pins
should either be disabled before entering Power-down or they should not be left floating.
Clock Source A
External Crystal or
Resonator
External Clock
Internal RC
Oscillator
On AT89LP51ID2 OSCB requires 0, 1 or 2 I/O pins depending on the Clock Source B setting. Dis-
abling OSCB (OscbEn = 0) frees up the OSCB pins for general use. Disabling OSCA
(OscAEn = 0) does NOT free up the OSCA pins. OSCA must be configured for Internal RC mode
to use these pins even when running from OSCB only.
Table
AT89LP51RD2/ED2 I/O Pin Configurations
12-1.
Table
External Program Access
12-3. The Tristate-Port User Fuse (See
Yes (PSEN+ALE+P0+P2)
Yes (PSEN+ALE+P0+P2)
Yes (PSEN+ALE+P0+P2)
AT89LP51RD2/ED2/ID2 Preliminary
No
No
No
16-bit (ALE+RD+WR+P0+P2)
16-bit (ALE+RD+WR+P0+P2)
16-bit (ALE+RD+WR+P0)
8-bit (ALE+RD+WR+P0)
8-bit (ALE+RD+WR+P0)
8-bit (ALE+RD+WR+P0)
External Data Access
Yes (RD+WR)
Yes (RD+WR)
Yes (RD+WR)
No
No
No
No
No
No
Section 24.2 on page
Table 12-2
Number of I/O
using the reg-
Pins
18
20
27
19
38
19
21
28
20
39
20
22
29
21
40
190)
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