CY7C1361C-133AXI Cypress Semiconductor Corp, CY7C1361C-133AXI Datasheet - Page 10

• Manufacturer Part Number: CY7C1361C-133AXI
• Description: IC SRAM 9MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1361C-133AXI

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 250 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t
The CY7C1361C/CY7C1363C supports secondary cache in
systems using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user-selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deasserted
during this first cycle). The address presented to the address
inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
at the data outputs a maximum to t
ignored if CE
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW
inputs are asserted active (see
on page 12
next clock rise, the appropriate data will be latched and written
into the device.Byte writes are allowed. All I/Os are tristated
during a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the I/Os
must be tristated prior to the presentation of data to DQs. As a
safety precaution, the data lines are tristated once a write cycle
is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
Document Number: 38-05541 Rev. *J
Note
4. CE
3
is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
X
) are ignored during this first clock cycle. If the write
CDV
for appropriate states that indicate a write) on the
1
is HIGH.
) is 6.5 ns (133 MHz device).
1
, CE
1
, CE
Partial Truth Table for Read/Write
X
2
) inputs. A global write enable
, CE
2
CDV
, and CE
1
, CE
3
1
after clock rise. ADSP is
[4]
, CE
2
are all asserted active
, and CE
3
2
[4]
, CE
are all asserted
3
[4]
3
[4]
) and an
are all
1
is
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ
specified address location. Byte writes are allowed. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the
presentation of data to DQ
lines are tristated once a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1361C/CY7C1363C provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter is
fed by A
order. The burst order is determined by the state of the MODE
input. A LOW on MODE will select a linear burst sequence. A
HIGH on MODE selects an interleaved burst order. Leaving
MODE unconnected causes the device to default to a interleaved
burst sequence.
Table 1. Interleaved Burst Address Table
(MODE = Floating or V
Table 2. Linear Burst Address Table (MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the ‘sleep’ mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the ‘sleep’ mode. CE
CE
of t
Address
Address
3
ZZREC
A1: A0
A1: A0
[4]
First
First
, ADSP, and ADSC must remain inactive for the duration
00
01
10
00
01
10
11
11
[1:0]
after the ZZ input returns LOW.
, and can follow either a linear or interleaved burst
Address
Address
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
CY7C1361C/CY7C1363C
DD
)
s
. As a safety precaution, the data
Address
Address
A1: A0
A1: A0
Third
Third
10
00
01
10
00
01
11
11
[A:D]
is written into the
Address
Address
Page 10 of 34
Fourth
A1: A0
Fourth
A1: A0
11
10
01
00
11
00
01
10
1
, CE
X
2
[+] Feedback
)
,