CY7C1361C-133AXI Cypress Semiconductor Corp, CY7C1361C-133AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1361C-133AXI
• Description: IC SRAM 9MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1361C-133AXI

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 250 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin Definitions
Document Number: 38-05541 Rev. *J
MODE
V
V
V
V
TDO
TDI
TMS
TCK
NC
V
DD
DDQ
SS
SSQ
SS
/DNU
Name
JTAG serial output
I/O power supply Power supply for the I/O circuitry.
JTAG serial input
JTAG serial input
(continued)
Power supply
Ground/DNU
synchronous
synchronous
synchronous
I/O ground
Ground
JTAG-
Input-
static
clock
I/O
–
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being used, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being used, this pin can be left floating or connected to V
up resistor. This pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being used, this pin can be disconnected or connected to V
not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must
be connected to V
No connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M,
and 1G are address expansion pins and are not internally connected to the die.
This pin can be connected to ground or should be left floating.
SS
. This pin is not available on TQFP packages.
Description
CY7C1361C/CY7C1363C
DD
DD
through a pull
. This pin is
Page 9 of 34
DD
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