CY7C038V-15AC Cypress Semiconductor Corp, CY7C038V-15AC Datasheet

IC SRAM 1.152MBIT 15NS 100LQFP

CY7C038V-15AC

Manufacturer Part Number
CY7C038V-15AC
Description
IC SRAM 1.152MBIT 15NS 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C038V-15AC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
1.152M (64K x 18)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1170

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C038V-15AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
025/0251
Features
Notes:
Cypress Semiconductor Corporation
1.
2.
• True Dual-Ported memory cells which allow simulta-
• 32K x 16 organization (CY7C027V)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V)
• 64K x 18 organization (CY7C038V)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
R/W
UB
CE
CE
OE
I/O
I/O
A
A
CE
OE
R/W
SEM
BUSY
INT
UB
LB
LB
neous access of the same memory location
— Active: I
— Standby: I
0L
0L
I/O
I/O
L
8/9L
0L
L
0L
1L
L
L
L
L
L
–A
–A
L
8
0
L
L
L
–I/O
–I/O
–I/O
L
[3]
14/15L
[3]
14/15L
–I/O
[4]
Logic Block Diagram
15
7
[2]
7/8L
for x16 devices; I/O
for x16 devices; I/O
[1]
15/17L
CC
SB3
= 115 mA (typical)
CE
= 10 A (typical)
15/16
L
For the most recent information, visit the Cypress web site at www.cypress.com
8/9
8/9
0
9
–I/O
–I/O
8
Address
17
Decode
for x18 devices.
15/16
for x18 devices.
3901 North First Street
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
3.
4.
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70V27
ter/Slave chip select when using more than one device
between ports
Control
A
BUSY is an output in master mode and an input in slave mode.
0
I/O
–A
14
for 32K; A
San Jose
3.3V 32K/64K x 16/18
Dual-Port Static RAM
0
–A
Address
Decode
15
15/16
for 64K devices.
CA 95134
CY7C027V/028V
CY7C037V/038V
15/16
8/9
8/9
CE
R
November 21, 2000
I/O
8/9L
I/O
A
A
408-943-2600
[4]
0R
0R
–I/O
0L
–A
–A
–I/O
[3]
[3]
BUSY
SEM
R/W
CE
CE
15/17R
14/15R
14/15R
R/W
[1]
INT
UB
LB
OE
OE
CE
UB
LB
[2]
7/8R
0R
1R
R
R
R
R
R
R
R
R
R
R
R
R

Related parts for CY7C038V-15AC

CY7C038V-15AC Summary of contents

Page 1

... CMOS for optimum speed/power • High-speed access: 15/20/25 ns • Low operating power — Active: I ...

Page 2

... Two ports are provided, permitting independent, asynchro- nous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM ...

Page 3

... Typical Standby Current for I (mA) (Both ports SB1 TTL level) Typical Standby Current for (Both ports SB3 CMOS level) Note: 6. This pin is NC for CY7C037V. 100-Pin TQFP (Top View CY7C038V (64K x 18) CY7C037V (32K x 18 CY7C027V/028V CY7C037V/038V -15 15 125 CY7C027V/028V CY7C037V/038V ...

Page 4

... Power Applied .............................................– +125 C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................–0. Note: 7. Pulse width < 20 ns. 8. Industrial parts are available in CY7C028V and CY7C038V only. Description Chip Enable (CE is LOW when CE 0 Read/Write Enable Output Enable Address (A –A for 32K ...

Page 5

Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage OH (V =Min –4.0 mA Output LOW Voltage (V =Min Input HIGH Voltage IH V Input LOW Voltage IL ...

Page 6

Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [12 LOW to Data Valid ACE t OE LOW to ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description [17] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t SEM Flag Update Pulse (OE or SEM) SOP t SEM Flag Write to Read Time SWRD ...

Page 8

Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I ...

Page 9

Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [29,30 R/W NOTE 32 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [29,30 R/W DATA IN Notes: 25. ...

Page 10

Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...

Page 11

Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 38 LOW. ...

Page 12

Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...

Page 13

Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R [41] t INS Right Side Clears INT : R ADDRESS R/W R ...

Page 14

... HIGH during SEM LOW). A address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port ...

Page 15

Table 1. Non-Contending Read/Write Inputs CE R ...

Page 16

... Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C037V-15AC 20 CY7C037V-20AC 25 CY7C037V-25AC 64K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C038V-15AC 20 CY7C038V-20AC CY7C038V-20AI 25 CY7C038V-25AC Document #: 38–00670–*D Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 ...

Page 17

... Package Diagram © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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