CY7C038V-20AXI Cypress Semiconductor Corp, CY7C038V-20AXI Datasheet

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... Complementary metal oxide semiconductor ■ (CMOS) for optimum speed and power High speed access: 15, 20, and 25 ns ■ ...

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Contents Pin Configurations ........................................................... 3 Pin Configurations (continued) ........................................ 4 Selection Guide ................................................................ 4 Pin Definitions .................................................................. 5 Architecture ...................................................................... 5 Functional Description ..................................................... 5 Write Operation ........................................................... 5 Read Operation ........................................................... 5 Interrupts ..................................................................... 5 Busy ............................................................................ 6 Master/Slave ...

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Pin Configurations 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [6] A15L LBL 10 UBL 11 CE0L 12 CE1L 13 SEML 14 VCC 15 R/WL 16 OEL ...

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... Typical standby current for I (Both ports TTL level) SB1 Typical standby current for I (Both ports CMOS level) SB3 Note 7. This pin is NC for CY7C037AV. Document #: 38-06078 Rev. *D Figure 2. 100-Pin TQFP (Top View CY7C038V (64K x 18) CY7C037AV (32K x 18 -15 15 125 35 10 A CY7C027V/027AV/028V CY7C037AV/038V 80 ...

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Pin Definitions Left Port Right Port R/W R –A A –A 0L 15L 0R 15R I/O –I/O I/O –I/O 0L 17L 0R 17R ...

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Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port ...

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... Input capacitance IN C Output capacitance OUT Notes 8. Pulse width < 20 ns. 9. Industrial parts are available in CY7C028V and CY7C038V, CY7C027V/027AV only. 10 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level standby I MAX ...

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... This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11. Document #: 38-06078 Rev. *D Figure 3. AC Test Loads and Waveforms = 250  OUTPUT 1 (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 90% 90% 10% 10%   [12] CY7C027V/027AV/028V/ CY7C037AV/CY7C038V -15 Min Max 15 – – – – 15 – – – – – – – 15 – ...

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... Timing during CC after V reaches the CC Parameter ICC DR1 Figure 11 –t (actual –t (actual). WDD PWE DDD SD CY7C027V/027AV/028V CY7C037AV/038V CY7C037AV/CY7C038V -20 -25 Min Max Min Max 0 – 0 – – 12 – – 3 – – 40 – 50 – 30 – 35 – 20 – 20 – ...

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Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...

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Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32,33 R/W NOTE 35 DATA OUT DATA IN Figure 8. Write Cycle No Controlled Timing ADDRESS [32,33 R/W ...

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Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Figure 10. Timing Diagram of Semaphore Contention A – R/W L ...

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Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41. CE ...

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Switching Waveforms (continued) Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Figure 14. Busy Timing ...

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Switching Waveforms (continued) Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R [44] t INS Right Side Clears INT : R ADDRESS R INT ...

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Table 1. Non-Contending Read/Write Inputs CE R ...

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... Ordering Code 20 CY7C037AV-20AXC 64K x18 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C038V-20AI CY7C038V-20AXI Document #: 38-06078 Rev. *D Package Name Package Type A100 100-Pin Pb-free Thin Quad Flat Pack A100 100-Pin Pb-free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...

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Ordering Code Definition Document #: 38-06078 Rev Operating Range C = Com m ercial I = Industrial free (RoHS Com pliant) Package: A=TQFP Speed Grade : 15ns/20ns/25ns ...

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Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06078 Rev. *D CY7C027V/027AV/028V CY7C037AV/038V 51-85048 *D Page [+] Feedback ...

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Acronyms Acronym Description CMOS complementary metal oxide semiconductor TQFP thin quad plastic flatpack I/O input/output SRAM static random access memory Document #: 38-06078 Rev. *D CY7C027V/027AV/028V CY7C037AV/038V Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V ...

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Document History Page Document Title: CY7C027V/027AV/CY7C028V/037AV/038V 3.3 V 32K/64K X 16/18 DUAL PORT STATIC RAM Document Number: 38-06078 Orig. of Rev. ECN No. Change ** 237626 YDT *A 259110 JHX *B 2623540 VKN/PYRS *C 2897217 RAME *D 3093542 ADMU Document ...

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