CY7C038V-20AXI Cypress Semiconductor Corp, CY7C038V-20AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C038V-20AXI
• Description: IC,SRAM,64KX18,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C038V-20AXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1.152M (64K x 18)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Data Retention Mode
The CY7C027V/027AV/028V and CY7037AV/038V are de-
signed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following
rules ensure data retention:
Document #: 38-06078 Rev. *D
1. Chip Enable (CE) must be held HIGH during data retention, within
2. CE must be kept between V
3. The RAM can begin operation >t
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
17. Test conditions used are Load 2
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to
20. Test conditions used are Load 1.
21. t
22. CE = V
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
Busy Timing
Interrupt Timing
Semaphore Timing
Parameter
V
the power up and power down transitions
minimum operating voltage (3.0 V)
to
CC
BDD
[21]
[21]
[21]
Figure
[17, 18]
[17, 18]
to V
is a calculated parameter and is the greater of t
CC
CC
11.
, V
in
– 0.2 V
= GND to V
[19]
Data hold from write end
R/W LOW to High Z
R/W HIGH to Low Z
Write pulse to data delay
Write data valid to read data valid
BUSY LOW from address match
BUSY HIGH from address mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port setup for priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to data valid
INT set time
INT reset time
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
[19]
CC
, T
A
= 25 C. This parameter is guaranteed but not tested.
CC
– 0.2 V and 70% of V
Description
Over the Operating Range
RC
WDD
after V
–t
PWE
(actual) or t
CC
reaches the
CC
DDD
during
–t
SD
[12]
(actual).
(continued)
Min
Timing
V
13
10
CE
ICC
0
–
3
–
–
–
–
–
–
5
0
–
–
–
5
5
–
CC
Parameter
DR1
-15
Max
10
30
25
15
15
15
15
15
15
15
15
–
–
–
–
–
–
–
–
Figure 11
CY7C027V/027AV/028V/
CY7C037AV/CY7C038V
3.0 V
Min
waveform.
15
10
At VCC
0
–
3
–
–
–
–
–
–
5
0
–
–
–
5
5
–
Data Retention Mode
Test Conditions
V
CC
-20
CY7C027V/027AV/028V
V
to V
CC
DR
Max
12
40
30
20
20
20
16
20
20
20
20
2.0 V
CC
–
–
–
–
–
–
–
–
= 2 V
– 0.2 V
CY7C037AV/038V
Min
17
12
[22]
0
–
3
–
–
–
–
–
–
5
0
–
–
–
5
5
–
3.0 V
-25
Max
Max
50
15
50
35
20
20
20
17
25
20
20
25
–
–
–
–
–
–
–
–
V
t
IH
RC
Page 9 of 22
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A
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