SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet

SST89E554RC-40-C-PI

Manufacturer Part Number

SST89E554RC-40-C-PI

Description

8-bit Microcontrollers - MCU 32KB+8KB 40ns

Manufacturer

Microchip Technology

Datasheet

1.SST89E564RD-40-I-NJE.pdf (90 pages)

Specifications of SST89E554RC-40-C-PI

Core

8051

Data Bus Width

8 bit

Maximum Clock Frequency

40 MHz

Program Memory Size

32 KB

Data Ram Size

1 KB

On-chip Adc

Operating Supply Voltage

4.5 V to 5.5 V

Package / Case

PDIP-40

Mounting Style

Through Hole

Data Rom Size

128 B

Interface Type

SPI, UART

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Number Of Programmable I/os

Number Of Timers

16 bit

On-chip Dac

Processor Series

FlashFlex

Program Memory Type

Flash

Supply Voltage - Max

5.5 V

Supply Voltage - Min

4.5 V

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

SST89E554RC-40-C-PI

Manufacturer:

FREESCALE

Quantity:

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FEATURES:

• 8-bit 8051-Compatible Microcontroller (MCU)

• SST89E564RD/SST89E554RC Operation

• SST89V564RD/SST89V554RC Operation

• Total 1 KByte Internal RAM (256 Byte + 768 Byte)

• Dual Block SuperFlash EEPROM

• Support External Address Range up to 64

• Three High-Current Drive Port 1 pins

• Three 16-bit Timers/Counters

PRODUCT DESCRIPTION

The SST89E564RD, SST89V564RD, SST89E554RC, and

SST89V554RC are members of the FlashFlex family of 8-bit

microcontroller products designed and manufactured with

SST’s patented and proprietary SuperFlash CMOS semi-

conductor process technology. The split-gate cell design

and thick-oxide tunneling injector offer significant cost and

reliability benefits for our customers. The devices use the

8051 instruction set and are pin-for-pin compatible with stan-

dard 8051 microcontroller devices.

The devices come with 72/40 KByte of on-chip flash

EEPROM program memory which is partitioned into 2

independent program memory blocks. The primary Block 0

occupies 64/32 KByte of internal program memory space

and the secondary Block 1 occupies 8 KByte of internal

program memory space.

The 8-KByte secondary flash block can be mapped to the

lowest location of the 64-/32-KByte address space; it can

also be hidden from the program counter and used as an

independent EEPROM-like data memory.

S71207-08-EOL

with Embedded SuperFlash Memory

– Fully Software Compatible

– Development Toolset Compatible

– Pin-For-Pin Package Compatible

– 0 to 40 MHz at 5V

– 0 to 33 MHz at 3V

– SST89E564RD/SST89V564RD:

– SST89E554RC/SST89V554RC:

– Individual Block Security Lock with SoftLock

– Concurrent Operation during

– Memory Overlay for Interrupt Support

KByte of Program and Data Memory

64 KByte primary block + 8 KByte secondary

block (128-Byte sector size for both blocks)

32 KByte primary block + 8 KByte secondary

block (128-Byte sector size for both blocks)

In-Application Programming (IAP)

during IAP

1/07

SST89E564RD / SST89V564RD

SST89E554RC / SST89V554RC

FlashFlex MCU

The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.

• Full-Duplex, Enhanced UART

• Eight Interrupt Sources at 4 Priority Levels

• Programmable Watchdog Timer (WDT)

• Programmable Counter Array (PCA)

• Four 8-bit I/O Ports (32 I/O Pins)

• Second DPTR register

• Low EMI Mode (Inhibit ALE)

• SPI Serial Interface

• Standard 12 Clocks per cycle, the device has an

• TTL- and CMOS-Compatible Logic Levels

• Brown-out Detection

• Low Power Modes

• Temperature Ranges:

• Packages Available

In addition to the 72/40 KByte of EEPROM on-chip pro-

gram memory and 1024 x8 bits of on-chip RAM, the

devices can address up to 64 KByte of external program

memory and up to 64 KByte of external RAM.

The flash memory blocks can be programmed via a stan-

dard 87C5x OTP EPROM programmer fitted with a special

adapter and the firmware for SST’s devices. During power-

on reset, the devices can be configured as either a slave to

an external host for source code storage or a master to an

external host for an in-application programming (IAP) oper-

ation. The devices are designed to be programmed in-sys-

tem and in-application on the printed circuit board for

maximum flexibility. The devices are pre-programmed with

an example of the bootstrap loader in memory, demonstrat-

ing the initial user program code loading or subsequent

user code updating via an IAP operation. A sample boot-

strap loader is available for the user’s reference and conve-

nience only; SST does not guarantee its functionality or

usefulness. Chip-Erase or Block-Erase operations will

erase the pre-programmed sample code.

– Framing Error Detection

– Automatic Address Recognition

option to double the speed to 6 clocks per cycle.

– Power-down Mode with External Interrupt Wake-up

– Idle Mode

– Commercial (0°C to +70°C)

– Industrial (-40°C to +85°C)

– 40-contact WQFN

– 44-lead PLCC

– 40-pin PDIP (Port 4 feature not available)

– 44-lead TQFP

– Non-Pb (lead-free) packages available

These specifications are subject to change without notice.

EOL Data Sheet

Related parts for SST89E554RC-40-C-PI

SST89E554RC-40-C-PI Summary of contents

Page 1

... KByte of Program and Data Memory • Three High-Current Drive Port 1 pins • Three 16-bit Timers/Counters PRODUCT DESCRIPTION The SST89E564RD, SST89V564RD, SST89E554RC, and SST89V554RC are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semi- conductor process technology ...

Page 2

... TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 Timer Set- 5.3 Programmable Clock-Out 6.0 SERIAL I 6.1 Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.0 PROGRAMMABLE COUNTER ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 PCA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3 Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1 Hard Lock ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 2 FlashFlex MCU S71207-08-EOL 1/07 ...

Page 3

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.4 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 Software Reset 10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.0 SYSTEM CLOCK AND CLOCK OPTIONS 12.1 Clock Input Options and Recommended Capacitor Values for Oscillator . . . . . . . . . . . . . . . . . . . . . . 66 12 ...

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... FIGURE 13-10: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 FIGURE 13-11: I Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DD FIGURE 13-12: I Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DD FIGURE 13-13: I Test Condition, Power-down Mode FIGURE 13-14: Read- FIGURE 13-15: Select-Block1 / Select-Block0 (For SST89E/V564RD only ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 4 FlashFlex MCU S71207-08-EOL 1/07 ...

Page 5

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC FIGURE 13-16: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 FIGURE 13-17: Block-Erase for SST89E/V564RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 FIGURE 13-18: Block-Erase for SST89E/V554RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 FIGURE 13-19: Sector-Erase FIGURE 13-20: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 FIGURE 13-21: Prog-SB1 / Prog-SB2 / Prog-SB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 FIGURE 13-22: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 FIGURE 13-23: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E/V564RD . . . . . . . . . . . . . . 14 TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E/V554RC ...

Page 6

... TABLE 13-6: DC Electrical Characteristics for SST89E564RD/554RC . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TABLE 13-7: DC Electrical Characteristics for SST89V564RD/554RC . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TABLE 13-8: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 TABLE 13-9: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TABLE 13-10: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TABLE 13-11: External Mode Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . 79 TABLE 15-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 6 FlashFlex MCU S71207-08-EOL 1/07 ...

Page 7

... Flash Control Unit Block 1 I/O Port 0 Block Security I/O Port Lock I/O Port 2 Timer 0 (16-bit) I/O Port 3 Timer 1 (16-bit) SPI Timer 2 (16-bit) 8-bit Enhanced PCA UART 32K x8 for SST89E554RC and SST89V554RC 7 EOL Data Sheet Interrupt 8 Interrupts Control RAM I I/O 8 I/O 8 I/O 1207 B1.3 S71207-08-EOL 1/07 ...

Page 8

... MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 FIGURE 2- SSIGNMENTS FOR ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 40 1 Top View (contacts facing down) 40- WQFN CONTACT 8 FlashFlex MCU P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2 ...

Page 9

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC (CEX1 / SS#) P1.4 (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 FIGURE 2- SSIGNMENTS FOR (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 FIGURE 2- SSIGNMENTS FOR ©2007 Silicon Storage Technology, Inc. 40 (T2) P1 (T2 EX) P1 (ECI) P1 ...

Page 10

... EOL Data Sheet (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 FIGURE 2- SSIGNMENTS FOR ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 44-lead PLCC Top View ...

Page 11

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 2.1 Pin Descriptions TABLE 2- ESCRIPTIONS 1 Symbol Type Name and Functions P0[7:0] I/O Port 0: Port 8-bit open drain bi-directional I/O port output port each pin can sink several LS TTL inputs. Port 0 pins that have ‘1’s written to them float, and in this state can be used as high-impedance inputs ...

Page 12

... ONTINUED emitted at a constant rate of 1/6 the crystal fre- 4 and can be used for external timing and clocking. One ALE pulse is skipped during 12 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC in order to enable the device to SS for internal pro e.g. for ALE pin. DD S71207-08-EOL 2 of 12V ...

Page 13

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 3.0 MEMORY ORGANIZATION The device has separate address spaces for program and data memory. 3.1 Program Flash Memory There are two internal flash memory blocks in the device. The primary flash memory block (Block 0) has 64/32 KByte. The secondary flash memory block (Block 1) has 8 KByte ...

Page 14

... RGANIZATION FOR ROGRAM EMORY LOCK WITCHING FOR ROGRAM EMORY LOCK WITCHING FOR 14 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC EA SFCF[1:0] = 10, 11 FFFFH External 32 KByte 8000H 7FFFH 32 KByte Block 0 0000H 1207 F03.2 SST89E/V564RD SST89E/V554RC S71207-08-EOL T3-1.1 1207 T3-2.0 1207 1/07 ...

Page 15

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 3.2.1 Reset Configuration of Program Memory Block Switching Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0 and/or SC1. The SC0 and SC1 bits are programmed via an external host mode command or an IAP Mode com- mand ...

Page 16

... The stack pointer may not be located in any part of the expanded RAM. RD#, WR# EXTRAM EMORY WITH ADDR >= 0300H RD# / WR# asserted RD# / WR# asserted 16 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC BIT MOVX @Ri MOVX A, @Ri ADDR = Any RD# / WR# not asserted RD# / WR# asserted S71207-08-EOL 1 T3-5.0 1207 1/07 ...

Page 17

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 2FFH Expanded RAM 768 Bytes (Indirect Addressing) 000H 2FFH Expanded RAM 000H FIGURE 3-3: I NTERNAL AND ©2007 Silicon Storage Technology, Inc. FFH (Indirect Addressing) Upper 128 Bytes Internal RAM 80H 7FH Lower 128 Bytes Internal RAM (Indirect & ...

Page 18

... CCAPM1 CCAPM2 RCAP2L RCAP2H TL2 SFCM SFAL SFAH SPSR AUXR1 TL0 TL1 TH0 DPL DPH 18 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC External Data Memory 1207 F51.0 CCAP3H CCAP4H IPAH CCAP3L CCAP4L CCAPM3 CCAPM4 SPCR TH2 SFDT SFST IPH TH1 AUXR WDTD ...

Page 19

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 3-7: CPU SFR RELATED Direct Symbol Description Address 1 ACC Accumulator E0H Register F0H 1 PSW Program Status D0H Word SP Stack Pointer 81H DPL Data Pointer 82H Low DPH Data Pointer 83H High 1 IE Interrupt Enable ...

Page 20

... TF1 TR1 TF0 TR0 TH0[7:0] TL0[7:0] TH1[7:0] TL1[7:0] TF2 EXF2 RCLK TCLK EXEN2 - - - - TH2[7:0] TL2[7:0] RCAP2H[7:0] RCAP2L[7:0] 20 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC LSB WDTS WDT SWDT xxx00x00b LSB Timer 0 GATE C/ IE1 IT1 IE0 IT0 TR2 C/T2# CP/RL2 T2OE DCEN xxxxxx00b ...

Page 21

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 3-11: I SFR NTERFACE S Direct Symbol Description Address SBUF Serial Data Buffer 99H 1 SCON Serial Port Control 98H SADDR Slave Address A9H SADEN Slave Address B9H Mask SPCR SPI Control D5H Register SPSR SPI Status AAH ...

Page 22

... FCM5 FCM4 FCM3 SuperFlash Low Order Byte Address Register SuperFlash High Order Byte Address Register 22 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Reset Value - SWR BSEL x0xxxx00b Reset Value FCM2 FCM1 FCM0 Reset Value ...

Page 23

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC SuperFlash Data Register (SFDT) Location 7 6 B5H Symbol Function SFDT Mailbox register for interfacing with flash memory block. (Data register). SuperFlash Status Register (SFST) (Read Only Register) Location 7 6 B6H SB1_i SB2_i Symbol Function SB1 ...

Page 24

... Timer 0 Interrupt Enable. EX0 External 0 Interrupt Enable. Interrupt Enable A (IEA) Location 7 6 E8H - - Symbol Function EBO Brown-out Interrupt Enable Enable the interrupt 0 = Disable the interrupt ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC ET2 ES ET1 EX1 EBO 24 FlashFlex MCU 2 1 ...

Page 25

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Interrupt Priority (IP) Location 7 6 B8H - PPC Symbol Function PPC PCA interrupt priority bit. PT2 Timer 2 interrupt priority bit. PS Serial Port interrupt priority bit. PT1 Timer 1 interrupt priority bit. PX1 External interrupt 1 priority bit. PT0 Timer 0 interrupt priority bit. ...

Page 26

... Hardware sets the flag on watchdog overflow. WDT Watchdog timer refresh. 0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a watchdog timer refresh. SWDT Start watchdog timer. 0: Stop WDT. 1: Start WDT. ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC ...

Page 27

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Watchdog Timer Data/Reload Register (WDTD) Location 7 6 85H Symbol Function WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set. PCA Timer/Counter Control Register Location 7 6 D8H Bit addressable Symbol Function ...

Page 28

... Timer 0 overflow 1 3 External clock at ECI/P1.2 pin (max. rate = clock mode, f OSC = oscillator frequency 28 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Reset Value CPS0 ECF 00xxx000b / clock mode) OSC / clock mode) OSC / clock mode) OSC ...

Page 29

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC PCA Compare/Capture Module Mode Register Location 7 6 DAH - ECOM0 DBH - ECOM1 DCH - ECOM2 DDH - ECOM3 DEH - ECOM4 1. Not bit addressable Symbol Function - Not implemented, reserved for future use. Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate. ...

Page 30

... Silicon Storage Technology, Inc DORD MSTR CPOL CPHA SPR0 SCK = f divided by OSC 128 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Reset Value SPR1 SPR0 , is as follows: OSC Reset Value - - - 00xxxxxxb S71207-08-EOL 00H 1/07 ...

Page 31

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC SPI Data Register (SPDR) Location 7 6 86H Power Control Register (PCON) Location 7 6 87H SMOD1 SMOD0 Symbol Function SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. ...

Page 32

... SM1 Mode Description 0 0 Shift Register 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART = oscillator frequency 32 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Reset Value TI RI 00000000b 1 Baud Rate clock mode) or OSC f /12 (12 clock mode) OSC Variable f / /16 (6 clock mode) ...

Page 33

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Timer/Counter 2 Control Register (T2CON) Location 7 6 C8H TF2 EXF2 Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1 ...

Page 34

... ⇓ ⇓ Input High Voltage (XTAL, RST Don’t care Address low order byte; IH1 34 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 1 P3[5:4] P2[7] P2[6] P0[7:0] P2[5: ...

Page 35

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 4- XTERNAL OST Operation RST PSEN# Read- IH1 IL Chip-Erase V V IH1 IL Block-Erase V V IH1 IL Sector-Erase V V IH1 IL Byte-Program V V IH1 IL Byte-Verify (Read IH1 IL Prog-SC0 V V IH1 IL Prog-SC1 V V IH1 IL Prog-SB1 V V IH1 ...

Page 36

... The Byte-Verify command allows the user to verify that the device correctly performed an Erase or Program com- mand. This command will be disabled if any security locks are enabled. See Figure 13-23 for timing waveforms. 36 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC applies to SST89E564RD/ S71207-08-EOL 1/07 ...

Page 37

... SFCF[1] out of reset. Once programmed, SC1 can only be restored to an erased state via a Chip-Erase command. See Figure 13-22 for timing waveforms. Prog- SC1 is for SST89E554RC/SST89V554RC only. 4.1.4 External Host Mode Clock Source In external host mode, an internal oscillator will provide clocking for the device, and the oscillator is unaffected by the clock doubler logic. The on-chip oscillator will be turned on as the device enters external host mode ...

Page 38

... Any (Block 0) >= 2000H (Block 0) Any (Block 0) < 2000H (Block 1) From external >= 2000H (Block 0) From external < 2000H (Block 1) From external Any (Block 0) 38 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC SC0_i SB1_i SB2_i X X EDC_i Block Being Programmed 1 None Block 1 Block 0 1 None ...

Page 39

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 4.2.4 In-Application Programming Mode Commands All of the following commands can only be initiated in the IAP mode. In all situations, writing the control byte to the SFCM register will initiate all of the operations. All com- mands will not be enabled if the security locks are enabled on the selected memory block ...

Page 40

... F46.1 external code memory. Program SB1 MOV SFCM, #0FH or MOV SFCM, #8FH 40 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC IAP Enable ORL SFCF, #40H Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL MOV SFCM, #0CH SFDT register contains data 1207 F47.0 ...

Page 41

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 4.2.4.7 Prog-SC0, Prog-SC1 Prog-SC0 command is used to program the SC0 bit. This command only changes the SC0 bit and has no effect on BSEL bit until after a reset cycle. SC0 bit previously in un-programmed state can be pro- grammed by this command. The Prog-SC0 command should reside only in Block 1 or external code memory ...

Page 42

... X 7 0EH DI 7 0CH DO 0FH AAH 03H AAH 05H AAH 09H AAH 09H AAH 08H AAH 42 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC SFAH [7:0] SFAL [7: 5AH X 55H X SFAH [7:0] ...

Page 43

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 5.0 TIMERS/COUNTERS 5.1 Timers The device has three 16-bit registers that can be used as either timers or event counters. The three timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte ...

Page 44

... RB8 TI Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) BOF POF GF1 GF0 PD To UART framing error control B D LOCK IAGRAM 44 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC SCON RI (98H) PCON IDL (87H) 1207 F52.1 S71207-08-EOL 1/07 ...

Page 45

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC RXD D0 Start bit RI SMOD0=X FE SMOD0=1 FIGURE 6-2: UART T IMINGS IN RXD D0 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 FIGURE 6-3: UART T IMINGS IN ©2007 Silicon Storage Technology, Inc Data byte M 1 ODE Data byte ODES AND ...

Page 46

... Slave 1 SADDR = 1111 0001 SADEN = 1111 1010 GIVEN = 1111 0X0X ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Slave 2 SADDR = 1111 0011 SADEN = 1111 1001 GIVEN = 1111 0XX1 6.1.2.1 Using the Given Address to Select Slaves Any bits masked off from SADEN become a “don’t care” ...

Page 47

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Select Slave 3 Only Slave 2 Given Address Possible Addresses 1111 X0X1 The user could use the possible addresses above to select slave 3 only. Another combination could be to select slave 2 and 3 only as shown below. Select Slaves 2 & 3 Only Slaves 2 & ...

Page 48

... F CPHA = 0 ORMAT WITH CPHA = 1 ORMAT WITH 48 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC LSB 2 1 LSB 1207 F16 LSB 2 1 LSB 1207 F17.0 S71207-08-EOL 1/07 ...

Page 49

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 7.0 WATCHDOG TIMER The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and auto- matic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period ...

Page 50

... Timer 0 overflow /8) OSC 16 Bits Each Module 0 Module 1 Module 2 Module 3 Module OMPARE APTURE ODULES 50 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 6 Clock Mode f /6 OSC f /2 OSC Timer 0 overflow External clock at ECI pin (maximum rate = f /4) OSC T8-1.0 1207 P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1 ...

Page 51

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC The table below summarizes various clock inputs at two common frequencies. TABLE 8-2: PCA T /C IMER OUNTER PCA Timer/Counter Mode Mode 0: f /12 OSC Mode 1: 1 Mode 2: Timer 0 Overflows Timer 0 programmed in: 8-bit mode 16-bit mode 8-bit auto-reload Mode 3: External Input MAX 1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled. CMOD’ ...

Page 52

... APTURE ODULES Bit Address, Symbol, or Alternative Port Function MSB CCAP0H[7:0] CCAP0L[7:0] CCAP1H[7:0] CCAP1L[7:0] CCAP2H[7:0] CCAP2L[7:0] CCAP3H[7:0] CCAP3L[7:0] CCAP4H[7:0] CCAP4L[7:0] 52 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC RESET LSB S71207-08-EOL Value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H T8-4.0 1207 1/07 ...

Page 53

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 8-5: PCA M M ODULE ODES Without Interrupt enabled ECOMy CAPPy CAPNy MATy - User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate. ...

Page 54

... Figure 8-2) CCF4 CCF3 CCF2 CCF1 Capture TOGn PWMn ECCFn ODE 54 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC CCF0 PCA Interrupt PCA Timer/Counter CH CL CCAPnH CCAPnL 1207 F35.1 S71207-08-EOL 1/07 ...

Page 55

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 8.3.2 16-Bit Software Timer Mode The 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic intervals setup by setting both the ECOM and MAT bits in the module’s CCAPMn register. The PCA timer will be compared to the module’ ...

Page 56

... Figure 8- CCF4 CCF3 CCAPnL Match 16-bit Comparator CH CL ECOMn CAPPn CAPNn MATn UTPUT ODE 56 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC CCON CCF2 CCF1 CCF0 PCA Interrupt Toggle CCAPMn TOGn PWMn ECCFn n 1207 F37.2 S71207-08-EOL CEXn 1/07 ...

Page 57

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 8.3.4 Pulse Width Modulator The Pulse Width Modulator (PWM) mode is used to gener- ate 8-bit PWMs by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output is low. When CL ≥ ...

Page 58

... IMER ODULE ONLY 58 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC CCAPM4, #4CH; Module 4 in compare mode CCAP4L, #0FFH; Write to low byte first CCAP4H, #0FFH; Before PCA timer counts FFFF Hex, these compare ; values must be changed. CMOD, #40H; Set the WDTE bit to enable the ...

Page 59

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 9.0 SECURITY LOCK The security lock protects against software piracy and pre- vents the contents of the flash from being read by unautho- rized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. There are two different types of security locks in the device security lock system: hard lock and SoftLock ...

Page 60

... P P Hard Lock Hard Lock 60 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Security Type No Security Features are Enabled. MOVC instructions executed from external program memory are dis- abled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further pro- gramming of the flash is disabled ...

Page 61

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 9- ECURITY OCK CCESS Level SFST[7:5] 111b 4 (hard lock on both blocks) 011b/101b (hard lock on both blocks) 001b/110b (Block 0 = SoftLock, Block 1 = hard lock) 3 010b (SoftLock on both blocks) 100b 2 (SoftLock on both blocks) 000b 1 (unlock) 1. Location of MOVC or IAP instruction 2 ...

Page 62

... Please refer to Section 3.5, PCON register definition for detail information. For more information on system level design techniques, please review the Design Considerations for the SST FlashFlex Family Microcontroller application note. ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC V DD 10µF 8.2K FIGURE 10-1: P 10.2 Software Reset The software reset is executed by changing SFCF[1] (SWR) from “ ...

Page 63

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 10.4 Interrupt Priority and Polling Sequence The device supports eight interrupt sources under a four level priority scheme. Table 10-1 summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector ...

Page 64

... TF2 EXF2 Individual FIGURE 10- NTERRUPT TRUCTURE ©2007 Silicon Storage Technology, Inc. IP/IPH/IPA/IPAH IE & IEA Registers Registers IE0 IE1 Global Disable Enables 64 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Highest Priority Interrupt Interrupt Polling Sequence Lowest Priority Interrup 1207 F42.3 S71207-08-EOL 1/07 ...

Page 65

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 11.0 POWER-SAVING MODES The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and power-down, see Table 11-1. 11.1 Idle Mode Idle mode is entered setting the IDL bit in the PCON regis- ter ...

Page 66

... Oscillator XTAL1 Signal V SS External Clock Drive EATURES Standard Mode (x1) Max. External Clock Frequency (MHz FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC NC XTAL2 XTAL1 V SS 1207 F21.1 Clock Double Mode (x2) Clocks per Max. External Clock Frequency Machine Cycle (MHz S71207-08-EOL T12-2 ...

Page 67

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 13.0 ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...

Page 68

... Refer to PCI spec. ©2007 Silicon Storage Technology, Inc. T EST = 100 pF L T13-3.0 1207 OWER UP IMINGS =3.3V, Ta=25 °C, f=1 Mhz, other pins open) 68 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Minimum Units 100 µs 100 µs T13-4.2 1207 Test Condition Maximum I ...

Page 69

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 13.1 DC Electrical Characteristics TABLE 13- LECTRICAL HARACTERISTICS FOR T = -40°C +85° Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Input High Voltage (XTAL1, RST) IH1 V Output Low Voltage (Ports 1.5, 1.6, 1. Output Low Voltage (Ports ...

Page 70

... -60µ -200µ -3.2mA 0. 0.45 < MHz, 25°C 70 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC s of ALE and Ports 1 & 3. The noise due OL - 0.7 specification when DD 2) Min Max < 3.6 -0.5 0.7 DD < 3.6 0. < 3 ...

Page 71

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 13- LECTRICAL HARACTERISTICS FOR T = -40°C +85° Symbol Parameter I Power Supply Current DD IAP Mode @ 12 MHz @ 33 MHz Active Mode @ 12 MHz @ 33 MHz Idle Mode @ 12 MHz @ 33 MHz Power-down Mode (min Under steady state (non-transient) conditions, I ...

Page 72

... Typical Active I DD Typical Idle Internal Clock Frequency (MHz) (SST89V564RD/554RC) Maximum Active I Typical Active Internal Clock Frequency (MHz) (SST89E564RD/554RC) 72 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Maximum Idle Typical Idle S71207-08-EOL 1/07 ...

Page 73

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 13.2 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 13- LECTRICAL HARACTERISTICS T = -40°C +85° Symbol Parameter 1/T x1 Mode Oscillator Frequency CLCL ...

Page 74

... Instruction (program memory contents) L: Logic level LOW or ALE P: PSEN# For example Time from Address Valid to ALE Low AVLL T = Time from ALE Low to PSEN# Low LLPL ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC ( ONTINUED OF = 2.7-3.6V@33MH , 4.5-5.5V@40MH Z DD Oscillator 33 MHz (x1 Mode) ...

Page 75

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC T LHLL ALE T AVLL PSEN# PORT 0 PORT 2 FIGURE 13- XTERNAL ROGRAM T LHLL ALE PSEN# RD# T AVLL A0-A7 FROM RI or DPL PORT 0 PORT 2 FIGURE 13- XTERNAL ATA ©2007 Silicon Storage Technology, Inc. T LLIV T LLPL T PLIV T PLAZ T PXIZ T LLAX ...

Page 76

... DD T CHCX 0 0.1 T CLCX T CLCH T CLCL T CHCL D W RIVE AVEFORM 76 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC T WHLH T WHQX A0-A7 FROM PCL INSTR IN A8-A15 FROM PCH 1207 F29.4 Variable Min Max 0 40 0.35T 0.65T CLCL CLCL 0.35T 0.65T CLCL CLCL T13-9.2 1207 1207 F30 ...

Page 77

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 13-10 ERIAL ORT IMING Symbol Parameter T Serial Port Clock Cycle Time XLXL T Output Data Setup to Clock Rising Edge QVXH T Output Data Hold After Clock Rising Edge XHQX T Input Data Hold After Clock Rising Edge ...

Page 78

... Silicon Storage Technology, Inc. TO TESTER 1207 F41.0 XAMPLE F22.0 All other pins disconnected , FIGURE 13-13 1207 F23 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC RST EA# 89x564 (NC) XTAL2 XTAL1 V SS 1207 F24.2 T ...

Page 79

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC TABLE 13-11 XTERNAL ODE 2,3 Parameter Reset Setup Time Read-ID Command Width PSEN# Setup Time Address, Command, Data Setup Time Chip-Erase Time Block-Erase Time Sector-Erase Time Program Setup Time Address, Command, Data Hold 4 Byte-Program Time Select-Block Program Time ...

Page 80

... SST89E564RD 90H for SST89V564RD 99H for SST89E554RC 98H for SST89V554RC ADS T PROG SST89E/V564RD ELECT LOCK OR 80 FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC T RD 0000b 0031H Device ID 1207 F05 PSB A5H/55H 1001b 1207 F06.1 ) ONLY S71207-08-EOL 1/07 ...

Page 81

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC T SU RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] FIGURE 13-16 HIP RASE Erases both flash memory blocks. Security lock is ignored and the security bits are erased too RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] FIGURE 13-17 LOCK RASE FOR Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. ...

Page 82

... PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] P3[5:4], P2[5:0] P1 FIGURE 13-19 ECTOR RASE Erases the addressed sector if the security lock is not activated on that flash memory block. ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC ADS T PROG SST89E/V554RC ADS T PROG 82 FlashFlex MCU 1101b AH 1207 F09 ...

Page 83

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC T SU RST PSEN# ALE/PROG# EA# P3[3] P3[5:4], P2[5: P3[7:6], P2[7:6] FIGURE 13-20 YTE ROGRAM Programs the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte-Program operation is only allowed when the security lock is not activated on that flash memory block. ...

Page 84

... EOL Data Sheet T SU RST PSEN# ALE/PROG# EA# P3[3] P3[5:4], P2[5:0] P3[7:6], P2[7:6] FIGURE 13-22: P -SC0 / P ROG ROG Programs the start-up configuration bit SC0/SC1. Only a Chip-Erase will erase a programmed SC0/SC1 bit. Prog-SC1 applies to SST89E554RC/SST89V554RC only RST PSEN# ALE/PROG# EA# P3[7:6], P2[7: P3[5:4], P2[5:0] FIGURE 13-23 YTE ERIFY Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. © ...

Page 85

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 14.0 PRODUCT ORDERING INFORMATION Device Speed Suffix1 SST89x5x4xx - XX - ©2007 Silicon Storage Technology, Inc. Suffix2 Package Attribute non- non-Pb / non-Sn contact (lead) finish: Nickel-Palladium with Gold flash outer layer Package Modifier contacts or pins ...

Page 86

... SST89V564RD-33-C-PI SST89V564RD-33-C-NJ SST89V564RD-33-C-PIE SST89V564RD-33-C-NJE SST89V564RD-33-I-PI SST89V564RD-33-I-NJ SST89V564RD-33-I-PIE SST89V564RD-33-I-NJE Valid combinations for SST89E554RC SST89E554RC-40-C-PI SST89E554RC-40-C-NJ SST89E554RC-40-I-PI SST89E554RC-40-I-NJ Valid combinations for SST89V554RC SST89V554RC-40-C-PI SST89V554RC-40-C-NJ SST89V554RC-40-I-PI SST89V554RC-40-I-NJ Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © ...

Page 87

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC 15.0 PACKAGING DIAGRAMS TOP VIEW Pin #1 6.00 ± 0.10 Note: 1. Complies with JEDEC JEP95 MO-220I, variant WJJD-5 except external paddle nominal dimensions. 2. From the bottom view, the pin #1 indicator may be either a 45-degree chamfer or a half-circle notch. 3. The external paddle is electrically connected to the die back-side and possibly to certain V This paddle can be soldered to the PC board ...

Page 88

... Coplanarity: 4 mils. 44 LEAD LASTIC EAD HIP ARRIER SST ACKAGE ODE ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC SIDE VIEW .147 .020 R. .158 MAX. .025 .042 R. x45˚ .045 .056 .013 .021 .500 .590 .026 .032 REF. ...

Page 89

... FlashFlex MCU SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Pin #1 Identifier 10.00 ± 0.10 12.00 ± 0.25 1.2 max. Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm. ...

Page 90

... Changed FlashFlex51 to FlashFlex globally 1. Fact sheet released as separate document. Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2007 Silicon Storage Technology, Inc. SST89E564RD / SST89V564RD SST89E554RC / SST89V554RC Description QVWX to Table 13-8 on page 73 and QVWX www ...

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