SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet - Page 59

• Manufacturer Part Number: SST89E554RC-40-C-PI
• Description: 8-bit Microcontrollers - MCU 32KB+8KB 40ns
• Manufacturer: Microchip Technology

Specifications of SST89E554RC-40-C-PI

• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: PDIP-40
• Mounting Style: Through Hole
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• On-chip Dac: No
• Processor Series: FlashFlex
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

FlashFlex MCU
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
9.0 SECURITY LOCK
The security lock protects against software piracy and pre-
vents the contents of the flash from being read by unautho-
rized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory. There are two different types of
security locks in the device security lock system: hard lock
and SoftLock.
9.1 Hard Lock
When hard lock is activated, MOVC or IAP instructions exe-
cuted from an unlocked or soft locked program address
space, are disabled from reading code bytes in hard locked
memory blocks (See Table 9-2). Hard lock can either lock
both flash memory blocks or just lock the 8 KByte flash
memory block (Block 1). All external host and IAP com-
mands except for Chip-Erase are ignored for memory
blocks that are hard locked.
9.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the soft locked memory block through in-
application programming mode under a predetermined
secure environment. For example, if Block 1 (8K) memory
block is locked (hard locked or soft locked), and Block 0
(64K for SST89E564RD/SST89V564RD) memory block is
soft locked, code residing in Block 1 can program Block 0.
The following IAP mode commands issued through the
Note:
©2007 Silicon Storage Technology, Inc.
FIGURE
P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1), N = Not Locked, L = Hard locked, S = Soft locked
9-1: S
ECURITY
L
UPP/LL
OCK
L
UPU/SS
EVELS
PPU/LS
UUU/NN
PUU/SS
PPP/LL
PUP/LL
59
command mailbox register, SFCM, executed from a
Locked (hard locked or soft locked) block, can be operated
on a soft locked block: Block-Erase, Sector-Erase, Byte-
Program and Byte-Verify.
In external host mode, SoftLock behaves the same as a
hard lock.
9.3 Security Lock Status
The three bits that indicate the device security lock
status are located in SFST[7:5]. As shown in Figure 9-
1 and Table 9-1, the three security lock bits control the
lock status of the primary and secondary blocks of
memory. There are four distinct levels of security lock
status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the
second level, although both blocks are now locked and
cannot be programmed, they are available for read
operation via Byte-Verify. In the third level, three differ-
ent options are available: Block 1 hard lock / Block 0
SoftLock, SoftLock on both blocks, and hard lock on
both blocks. Locking both blocks is the same as Level
2, Block 1 except read operation isn’t available. The
fourth level of security is the most secure level. It
doesn’t allow read/program of internal memory or boot
from external memory. For details on how to program
the security lock bits refer to the external host mode
and in-application programming sections.
UUP/LS
UPP/LL
Level 1
Level 2
Level 3
Level 4
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EOL Data Sheet
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