SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet - Page 16

• Manufacturer Part Number: SST89E554RC-40-C-PI
• Description: 8-bit Microcontrollers - MCU 32KB+8KB 40ns
• Manufacturer: Microchip Technology

Specifications of SST89E554RC-40-C-PI

• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: PDIP-40
• Mounting Style: Through Hole
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• On-chip Dac: No
• Processor Series: FlashFlex
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

EOL Data Sheet
Expanded RAM Access (Indirect Addressing only):
DPTR points to 0A0H and data in “A” is written to address
0A0H of the expanded RAM rather than external memory.
Access to external memory higher than 2FFH using the
MOVX instruction will access external memory (0300H to
FFFFH) and will perform in the same way as the standard
8051, with P0 and P2 as data/address bus, and P3.6 and
P3.7 as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will
be similar to the standard 8051. Using MOVX @Ri pro-
vides an 8-bit address with multiplexed data on Port 0.
Other output port pins can be used to output higher order
TABLE
©2007 Silicon Storage Technology, Inc.
EXTRAM = 0
EXTRAM = 1
1. Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH.
MOVX
AUXR
3-5: E
@DPTR, A
XTERNAL
RD# / WR# not asserted
RD# / WR# asserted
ADDR < 0300H
D
MOVX @DPTR, A or MOVX A, @DPTR
ATA
; DPTR contains 0A0H
M
EMORY
RD#, WR#
RD# / WR# asserted
RD# / WR# asserted
ADDR >= 0300H
WITH
16
EXTRAM
address bits. This provides external paging capabilities.
Using MOVX @DPTR generates a 16-bit address. This
allows external addressing up the 64K. Port 2 provides the
high-order eight address bits (DPH), and Port 0 multiplexes
the low order eight address bits (DPL) with data. Both
MOVX @Ri and MOVX @DPTR generates the necessary
read and write signals (P3.6 - WR# and P3.7 - RD#) for
external memory use. Table 3-5 shows external data mem-
ory RD#, WR# operation with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the
256 bytes of internal RAM (lower 128 bytes and upper 128
bytes). The stack pointer may not be located in any part of
the expanded RAM.
BIT
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
MOVX @Ri, A or MOVX A, @Ri
RD# / WR# not asserted
RD# / WR# asserted
ADDR = Any
FlashFlex MCU
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