AT25DF641-S3H-B Atmel, AT25DF641-S3H-B Datasheet - Page 14

• Manufacturer Part Number: AT25DF641-S3H-B
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 19 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 128
• Memory Configuration: 32K Pages X 256 Bytes
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 5ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In
addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched
into the internal buffer.
When the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within
the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is
internally self-timed and should take place in a time of t
The three address bytes and at least one complete byte of data must be clocked into the device before the
is deasserted, and the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”
on page 22) or locked down (see “Sector Lockdown” on page 28), then the Byte/Page Program command will not
be executed, and the device will return to the idle state once the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the t
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
Figure 7-3.
Atmel AT25DF641
SCK
SOI
CS
SI
CS
Dual-Input Byte Program
pin is deasserted, the device will take the data stored in the internal buffer and program it into the
HIG H-IMP E DANC E
MS B
1
0
CS
0
1
1
pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
2
OP C ODE
0
3
0
4
0
5
1
6
0
7
MS B
A
8
A
9
ADDR E S S B IT S A23-A0
A
10 11
A
A
12
A
PP
CS
or t
pin being deasserted on uneven byte boundaries, or
A
BP
29 30
A
if only programming a single byte.
CS
A
31 32
MS B
D 6
D 7
DAT A B Y T E
pin has been deasserted. The WEL bit in the
INP UT
D 4
D 5
33
D 2
D 3
34
D 0
D 1
35
BP
3680F–DFLASH–4/10
or t
PP
time to
CS
pin