AT25DF641-S3H-B Atmel, AT25DF641-S3H-B Datasheet - Page 27

• Manufacturer Part Number: AT25DF641-S3H-B
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 19 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 128
• Memory Configuration: 32K Pages X 256 Bytes
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 5ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.7.
3680F–DFLASH–4/10
Figure 8-5.
Protected States and the Write Protect (
The
status of the memory array. Instead, the
Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware
locking to be active, two conditions must be met-the
logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked.
Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be
locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the
Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the
protection status of a sector, the
reset back to the logical “0” state using the Write Status Register command. When resetting the SPRL bit back to
a logical “0”, it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector
Protection Registers remain soft-locked until after the Write Status Register command has been executed.
If the
reset the bit back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all
sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as
needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register.
When the
Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking
ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing
the SPRL bit to a logical “1” from a logical “0”, it is also possible to perform a Global Protect or Global Unprotect at
the same time by writing the appropriate values into bits five, four, three, and two of the first byte of the Status
Register.
Table 8-1 and Table 8-2 detail the various protection and locking states of the device.
Table 8-4.
Note:
SCK
SO
CS
SI
WP
WP
(Don't Care)
1. “n” represents a sector number.
pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown
W
pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to
WP
X
P
Read Sector Protection Register
Sector Protection Register States
pin is deasserted, or if the
MS B
HIG H-IMP E DANC E
0
0
0
1
1
2
OP C ODE
1
3
1
4
WP
1
5
Sector Protection Register
0
6
pin must first be deasserted, and the SPRL bit in the Status Register must be
0
7
MS B
A
8
WP
A
WP
9
ADDR E S S B IT S A23-A0
A
n
10 11
W
0
1
pin is permanently connected to V
(1)
pin, in conjunction with the SPRL (Sector Protection Registers
A
P
) Pin
A
12
A
WP
pin must be asserted and the SPRL bit must be in the
A
29 30
A
A
31 32
MS B
D
D
33
DAT A B Y T E
D
34
D
35
D
3 6
Atmel AT25DF641
D
37 38
CC
D
, the SPRL bit in the Status
D
39 40
Unprotected
MS B
D
Protected
Sector
D
n
(1)
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