EVAL-AD7450ASDZ

Manufacturer Part NumberEVAL-AD7450ASDZ
DescriptionData Conversion IC Development Tools EVALUATION BOARD I.C.
ManufacturerAnalog Devices
TypeADC
SeriesAD7450A
EVAL-AD7450ASDZ datasheet
 

Specifications of EVAL-AD7450ASDZ

RohsyesProductEvaluation Boards
Tool Is For Evaluation OfAD7450AInterface TypeSerial
Operating Supply Voltage2.7 V to 5.25 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 CFactory Pack Quantity1
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AD7440/AD7450A
AD7440/AD7450A to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
CS input allows easy interfacing
AD7440/AD7450A. The
between the TMS320C5x/C54x and the AD7440/AD7450A
without any glue logic required. The serial port of the
TMS320C5x/C54x is set up to operate in burst mode with
internal CLKx (Tx serial clock) and FSx (Tx frame sync). The
serial port control register (SPC) must have the following setup:
FO = 0, FSM = 1, MCM = 1, and TxM = 1. The format bit, FO,
may be set to 1 to set the word length to eight bits to implement
the power-down mode on the AD7440/AD7450A. The con-
nection diagram is shown in Figure 46. For signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C5x/C54x provide equidistant
sampling.
AD7440/
AD7450A*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 46. Interfacing to the TMS320C5x/C54
AD7440/AD7450A to DSP56xxx
The connection diagram in Figure 47 shows how the device can
be connected to the synchronous serial interface (SSI) of the
DSP56xxx family of DSPs from Motorola. The SSI is operated in
synchronous mode (SYN bit in CRB = 1) with internally
generated 1-word frame sync for both Tx and Rx (Bits FSL1 = 0
and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits
WL1 = 1 and WL0 = 0 in CRA. To implement power-down
mode on the AD7440/AD7450A, the word length can be
changed to 8 bits by setting Bits WL1 = 0 and WL0 = 0 in CRA.
For signal processing applications, it is imperative that the
frame synchronization signal from the DSP56xxx provide
equidistant sampling.
AD7440/
AD7450A*
SCLK
SDATA
CS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 47. Interfacing to the DSP56xxx
GROUNDING AND LAYOUT HINTS
The printed circuit board that houses the AD7440/AD7450A
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes
as it gives the best shielding. Digital and analog ground planes
should be joined in only one place, a star ground point
established as close to the GND pin on the AD7440/AD7450A
as possible. Avoid running digital lines under the devices
because this couples noise onto the die. The analog ground
plane should be allowed to run under the AD7440/AD7450A to
avoid noise coupling. The power supply lines to the
AD7440/AD7450A should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line.
Fast switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other sections of the board,
TMS320C5x/
C54x*
and clock signals should never run near the analog inputs.
CLKx
Avoid crossover of digital and analog signals. Traces on
CLKR
opposite sides of the board should run at right angles to each
DR
other. This reduces the effects of feedthrough through the
FSx
board. A microstrip technique is by far the best but is not
FSR
always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device.
EVALUATING THE AD7440/AD7450A
PERFORMANCE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the evaluation board
controller. The evaluation board controller can be used in
conjunction with the AD7440/AD7450A evaluation board, as
well as many other Analog Devices evaluation boards ending
with the CB designator, to demonstrate and evaluate the ac and
dc performance of the AD7440/AD7450A.
DSP56xxx*
The software allows the user to perform ac (fast Fourier
SCLK
transform) and dc (histogram of codes) tests on the device. See
SRD
the AD7440/AD7450A application note that accompanies the
SR2
evaluation kit for more information.
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