MT46H16M16LFBF-5 IT:H TR Micron Technology Inc, MT46H16M16LFBF-5 IT:H TR Datasheet - Page 13

• Manufacturer Part Number: MT46H16M16LFBF-5 IT:H TR
• Description: IC DDR SDRAM 256MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H16M16LFBF-5 IT:H TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2: VFBGA Ball Descriptions
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
RAS#, CAS#, WE#
LDQS, UDQS
UDM, LDM
BA0, BA1
DQ[15:0]
DQ[31:0]
DQS[3:0]
Symbol
(60-ball)
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
DM[3:0]
CK, CK#
A[12:0]
A[13:0]
V
V
CKE
V
CS#
V
DDQ
SSQ
DD
SS
output
output
Supply
Supply
Supply
Supply
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Description
Clock: CK is the system clock input. CK and CK# are differential clock inputs. All ad-
dress and control input signals are sampled on the crossing of the positive edge of
CK and the negative edge of CK#. Input and output data is referenced to the cross-
ing of CK and CK# (both directions of the crossing).
Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock sig-
nals, input buffers, and output drivers. Taking CKE LOW enables PRECHARGE power-
down and SELF REFRESH operations (all banks idle), or ACTIVE power-down (row
active in any bank). CKE is synchronous for all functions except SELF REFRESH exit.
All input buffers (except CKE) are disabled during power-down and self refresh
modes.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external bank selection on systems with multiple banks. CS# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command be-
ing entered.
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM balls are input-only, the DM loading
is designed to match that of DQ and DQS balls.
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0 and BA1 also determine which
mode register is loaded during a LOAD MODE REGISTER command.
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ or WRITE commands, to select one
location out of the memory array in the respective bank. During a PRECHARGE com-
mand, A10 determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE REGISTER command. The maximum address
range is dependent upon configuration. Unused address balls become RFU.
Data input/output: Data bus for x16 and x32.
Data strobe: Output with read data, input with write data. DQS is edge-aligned
with read data, center-aligned in write data. It is used to capture data.
DQ power supply.
DQ ground.
Power supply.
Ground.
13
256Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
©2008 Micron Technology, Inc. All rights reserved.
1