MT46H16M16LFBF-5 IT:H TR Micron Technology Inc, MT46H16M16LFBF-5 IT:H TR Datasheet - Page 20

• Manufacturer Part Number: MT46H16M16LFBF-5 IT:H TR
• Description: IC DDR SDRAM 256MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H16M16LFBF-5 IT:H TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications – I
Table 6: I
Notes 1–5 apply to all parameters/conditions in this table; V
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Parameter/Condition
Operating 1 bank active precharge current:
t
dress inputs are switching every 2 clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle, CKE is
LOW; CS is HIGH,
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle CKE =
HIGH; CS = HIGH;
switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle, CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Active power-down standby current: 1 bank active, CKE = LOW;
CS = HIGH;
ing; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac-
tive, CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active, CKE = HIGH; CS =
HIGH;
Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active,
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4;
tinuous READ bursts; I
every 2 clock cycles; 50% data changing each burst
Operating burst write: 1 bank active; BL = 4;
tinuous WRITE bursts; Address inputs are switching; 50% data
changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data bus
inputs are stable
Deep power-down current: Address and control balls are stable;
Data bus inputs are stable
CK (MIN); CKE is HIGH; CS is HIGH between valid commands; Ad-
t
CK =
DD
t
CK =
t
CK (MIN); Address and control inputs are switching;
Specifications and Conditions (x16)
t
t
t
CK (MIN); Address and control inputs are switch-
CK =
CK =
OUT
t
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
= 0mA; Address inputs are switching
t
t
RC =
t
CK =
CK =
DD
t
t
t
t
RFC = 110ns
RFC =
Parameters
RC (MIN);
t
CK (MIN); Con-
CK (MIN); Con-
t
REFI
DD
20
t
CK =
/V
Electrical Specifications – I
DDQ
256Mb: x16, x32 Mobile LPDDR SDRAM
Symbol
= 1.70–1.95V
I
I
I
I
I
I
I
I
I
I
I
DD2NS
DD3NS
DD2PS
DD3PS
DD4W
I
DD2N
DD3N
DD4R
I
DD5A
I
DD2P
DD3P
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD0
DD5
DD8
300
300
100
100
70
30
15
30
10
90
10
-5
5
3
8
300
300
-54
65
27
12
27
10
95
95
90
10
5
3
6
Max
300
300
60
25
25
10
90
90
90
10
©2008 Micron Technology, Inc. All rights reserved.
-6
5
5
3
5
DD
-75
300
300
50
20
20
10
85
85
90
10
5
5
3
3
Parameters
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6