MT47H32M8BP-5E:B TR Micron Technology Inc, MT47H32M8BP-5E:B TR Datasheet - Page 6

• Manufacturer Part Number: MT47H32M8BP-5E:B TR
• Description: IC DDR2 SDRAM 256MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H32M8BP-5E:B TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

List of Figures
Figure 1: 256Mb DDR2 Part Numbers .............................................................................................................. 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 64 Meg x 4 Functional Block Diagram .............................................................................................. 11
Figure 4: 32 Meg x 8 Functional Block Diagram .............................................................................................. 12
Figure 5: 16 Meg x 16 Functional Block Diagram ............................................................................................. 12
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 13
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 14
Figure 8: 84-Ball, FBGA Package (8mm x 14mm) – x16 .................................................................................... 17
Figure 9: 60-Ball, FBGA Package (8mm x 12mm) – x4, x8 ................................................................................. 18
Figure 10: Example Temperature Test Point Location ..................................................................................... 21
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 39
Figure 12: Differential Input Signal Levels ...................................................................................................... 40
Figure 13: Differential Output Signal Levels .................................................................................................... 42
Figure 14: Output Slew Rate Load .................................................................................................................. 43
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 44
Figure 16: Full Strength Pull-Up Characteristics ............................................................................................. 45
Figure 17: Reduced Strength Pull-Down Characteristics ................................................................................. 46
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 47
Figure 19: Input Clamp Characteristics .......................................................................................................... 48
Figure 20: Overshoot ..................................................................................................................................... 49
Figure 21: Undershoot .................................................................................................................................. 49
Figure 22: Nominal Slew Rate for
Figure 23: Tangent Line for
Figure 24: Nominal Slew Rate for
Figure 25: Tangent Line for
Figure 26: Nominal Slew Rate for
Figure 27: Tangent Line for
Figure 28: Nominal Slew Rate for
Figure 29: Tangent Line for
Figure 30: AC Input Test Signal Waveform Command/Address Balls ............................................................... 62
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 62
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 63
Figure 33: AC Input Test Signal Waveform (Differential) ................................................................................. 63
Figure 34: MR Definition ............................................................................................................................... 71
Figure 35: CL ................................................................................................................................................ 74
Figure 36: EMR Definition ............................................................................................................................. 75
Figure 37: READ Latency ............................................................................................................................... 78
Figure 38: WRITE Latency ............................................................................................................................. 78
Figure 39: EMR2 Definition ........................................................................................................................... 79
Figure 40: EMR3 Definition ........................................................................................................................... 80
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 82
Figure 42: Example: Meeting
Figure 43: Multibank Activate Restriction ....................................................................................................... 86
Figure 44: READ Latency ............................................................................................................................... 88
Figure 45: Consecutive READ Bursts .............................................................................................................. 89
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 90
Figure 47: READ Interrupted by READ ........................................................................................................... 91
Figure 48: READ-to-WRITE ............................................................................................................................ 91
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 92
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 92
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 DDR2 SDRAM
©2003 Micron Technology, Inc. All rights reserved.