MT46H32M32LFCG-5 IT:A Micron Technology Inc, MT46H32M32LFCG-5 IT:A Datasheet - Page 20

• Manufacturer Part Number: MT46H32M32LFCG-5 IT:A
• Description: IC DDR SDRAM 1GBIT 152VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M32LFCG-5 IT:A

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 1G (32M x 32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 152-VFBGA
• Organization: 32Mx32
• Density: 1Gb
• Address Bus: 13b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications – I
Table 7: I
Notes 1–5 apply to all the parameters/conditions in this table; V
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. K 07/09 EN
Parameter/Condition
Operating 1 bank active precharge current:
t
dress inputs are switching every 2 clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle; CKE =
HIGH; CS = HIGH;
switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Active power-down standby current: 1 bank active; CKE = LOW;
CS = HIGH;
ing; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac-
tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS =
HIGH;
Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4;
tinuous READ bursts; I
every 2 clock cycles; 50% data changing each burst
Operating burst write: 1 bank active; BL = 4;
tinuous WRITE bursts; Address inputs are switching; 50% data
changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data bus
inputs are stable
Typical deep power-down current at 25°C: Address and control
balls are stable; Data bus inputs are stable
CK (MIN); CKE is HIGH; CS is HIGH between valid commands; Ad-
t
CK =
DD
t
CK =
t
CK (MIN); Address and control inputs are switching;
Specifications and Conditions (x16)
t
t
t
CK (MIN); Address and control inputs are switch-
CK =
CK =
OUT
t
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
= 0mA; Address inputs are switching
t
t
RC =
t
CK =
CK =
DD
t
t
t
t
RFC = 138ns
RFC =
Parameters
RC (MIN);
t
CK (MIN); Con-
CK (MIN); Con-
t
REFI
20
t
CK =
Electrical Specifications – I
DD
/V
DDQ
Symbol
I
I
I
I
I
1Gb: x16, x32 Mobile LPDDR SDRAM
I
I
I
I
I
I
DD2NS
DD3NS
DD2PS
DD3PS
DD4W
I
DD2N
DD3N
DD4R
I
DD5A
I
DD2P
DD3P
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD0
DD5
DD8
= 1.70–1.95V
130
130
140
80
18
14
20
14
15
-5
125
125
140
-54
75
17
13
19
14
15
Max
600
600
3.6
3.6
10
115
115
140
70
15
18
14
15
©2007 Micron Technology, Inc. All rights reserved.
-6
8
DD
-75
105
105
140
60
12
16
12
14
8
Parameters
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6