M25PX32-VZM6F NUMONYX, M25PX32-VZM6F Datasheet - Page 36

• Manufacturer Part Number: M25PX32-VZM6F
• Description: IC FLASH 32MBIT 75MHZ 24TBGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX32-VZM6F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX32-VZM6FTR

6.9
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Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output
(DQ1), each bit being shifted out, at a maximum frequency f
Serial Clock (C).
The instruction sequence is shown in
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9.
1. Values of (b1, b0) after power-up are defined in
Figure 17. Read Lock Register (RDLR) instruction sequence and data-out sequence
DQ0
DQ1
b7-b2
Bit
b1
b0
C
S
Sector Lock Down
Sector Write Lock
Lock Register out
Bit name
0
1
High Impedance
2
Instruction
3
4
5
Value
‘1’
‘0’
‘1’
‘0’
6
(1)
7
MSB
23
The Write Lock and Lock Down bits cannot be changed.
Once a ‘1’ is written to the Lock Down bit it cannot be cleared
to ‘0’, except by a power-up.
The Write Lock and Lock Down bits can be changed by
writing new values to them.
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
Write, Program and Erase operations in this sector are
executed and will modify the sector contents.
8
Figure
22 21
9 10
24-bit address
Section 7: Power-up and
17.
Reserved
3
28 29 30 31 32 33 34 35
2
1
0
MSB
Function
7
C
, during the falling edge of
6
power-down.
Lock Register Out
5
4
3
36 37 38
2
1
0
39
AI13738