IDT70V25L25PFGI8 IDT, Integrated Device Technology Inc, IDT70V25L25PFGI8 Datasheet - Page 16

• Manufacturer Part Number: IDT70V25L25PFGI8
• Description: IC SRAM 128KBIT 25NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V25L25PFGI8

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (8K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 70V25L25PFGI8

NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
2. To ensure that the earlier of the two ports wins.
3. t
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
Timing Waveform of Write Port-to-Port Read and BUSY
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34
PORT-TO-PORT DELAY TIMING
BUSY TIMING (M/S = V
t
t
t
t
t
t
t
BUSY TIMING (M/S = V
t
t
t
t
BAA
BDA
BAC
BDC
APS
BDD
WH
WB
WH
WDD
DDD
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Symbol
BUSY (M/S = V
BDD
L
= CE
is a calculated parameter and is the greater of 0, t
DATA
DATA
IL
ADDR
ADDR
BUSY
for the reading port.
R
IL
R/W
OUT "B"
= V
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Dis able Time from Chip Enable HIGH
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write Hold After BUSY
BUSY Input to Write
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
(slave), BUSY is an input. Then for this example BUSY
IN "A"
IL.
IH
"A"
"A"
"B"
"B"
)".
IH
IL
)
)
t
APS
(1)
(4)
(5)
(5)
(1)
(3)
(2)
Parameter
(1)
APS
is ignored for M/S = V
WDD
– t
WP
(actual) or t
t
BAA
“A”
= V
MATCH
IL
IH
6.42
t
DDD
WC
16
(slave).
and BUSY
– t
DW
(actual).
“B”
Min.
t
____
____
____
____
____
____
____
12
12
70V35/34X15
WP
5
0
Com'l Ony
input is shown above.
MATCH
t
DW
Max.
Industrial and Commercial Temperature Ranges
____
____
____
____
t
15
15
15
15
18
30
25
WDD
VALID
Min.
____
____
____
____
____
____
____
15
15
70V35/34X20
5
0
t
DDD
Com'l
(6)
& Ind
(3)
(2,4,5)
Max.
____
____
____
____
20
20
20
30
45
35
t
17
BDA
t
DH
(M/S = V
Min.
____
____
____
____
____
____
____
17
17
70V35/34X25
5
0
Com'l Only
5624 drw 13
t
BDD
Max.
VALID
____
____
____
____
20
20
20
30
50
35
17
IH
5624 tbl 13
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns