IDT70V25L25PFGI8 IDT, Integrated Device Technology Inc, IDT70V25L25PFGI8 Datasheet - Page 23

• Manufacturer Part Number: IDT70V25L25PFGI8
• Description: IC SRAM 128KBIT 25NS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V25L25PFGI8

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 128K (8K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 70V25L25PFGI8

software. As an example, the semaphore can be used by one processor
to inhibit the other from accessing a portion of the Dual-Port SRAM or any
other shared resource.
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be accessed
at the same time with the only possible conflict arising from the simultaneous
writing of, or a simultaneous READ/WRITE of, a non-semaphore location.
Semaphores are protected against such ambiguous situations and may
be used by the system program to avoid any conflicts in the non-
semaphore portion of the Dual-Port SRAM. These devices have an
automatic power-down feature controlled by CE, the Dual-Port SRAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
multiple processors or controllers and are typically very high-speed
systems which are software controlled or software intensive. These
systems can benefit from a performance increase offered by the IDT70V35/
34 (IDT70V25/24)'s hardware semaphores, which provide a lockout
mechanism without requiring complex programming.
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V35/34 (IDT70V25/24) does not use its sema-
phore flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
24) in a separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts as
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
The Dual-Port SRAM features a fast access time, and both ports are
Systems which can best use the IDT70V35/34 (IDT70V25/24) contain
Software handshaking between processors offers the maximum in
An advantage of using semaphores rather than the more common
The semaphore logic is a set of eight latches which are independent
The semaphore flags are active LOW. A token is requested by writing
The eight semaphore flags reside within the IDT70V35/34 (IDT70V25/
6.42
23
a chip select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing a standard
static RAM. Each of the flags has a unique address which can be accessed
by either side through address pins A
semaphores, none of the other address pins has any effect.
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
When writing to a semaphore, only data pin D
When a semaphore flag is read, its value is spread into all data bits so
A sequence WRITE/READ must be used by the semaphore in order
It is important to note that a failed semaphore request must be followed
Industrial and Commercial Temperature Ranges
0
– A
2
. When accessing the
0
is used. If a LOW level