AT49LH00B4-33JC SL383 Atmel, AT49LH00B4-33JC SL383 Datasheet
AT49LH00B4-33JC SL383
Specifications of AT49LH00B4-33JC SL383
Related parts for AT49LH00B4-33JC SL383
AT49LH00B4-33JC SL383 Summary of contents
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... Green (Pb/Halide-free) Packaging Option 1. Description The AT49LH00B4 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec- ification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH00B4 to be used as a FWH with Intel chipsets LPC Flash with non-Intel chipsets ...
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... The memory array of the AT49LH00B4 can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16-Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top (upper- most) of the device’ ...
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... GPI4 [R/C] CLK 9 VCC [RST] RST [A9] GPI3 15 [A8] GPI2 16 [A7] GPI1 17 [A6] GPI0 18 [A5 [A4] TBL Designates A/A Mux Interface. AT49LH00B4 29 IC [IC] 28 GND VCC 24 INIT [OE] 23 FWH4/LFRAME [WE] 22 RES [RDY/BSY] 21 RES [I/O7] 40 GND 39 VCC 38 FWH4/LFRAME [WE] 37 INIT [OE] 36 RES [RDY/BSY] ...
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... Main Sector 9 Main Sector 8 Main Sector 7 Main Sector 6 Main Sector 5 Main Sector 4 Main Sector 3 Sub-sector 2 Sub-sector 1 Sub-sector 0 Sub-sector AT49LH00B4 4 TBL WP INIT FWH/LPC CONTROL LOGIC INTERFACE INTERFACE CONTROL AND LOGIC A/A MUX INTERFACE Type Size (Bytes) 64K 64K 64K 64K 64K 64K 64K ...
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... If the TBL pin is held high, then hardware write protection for the top boot sector will be disabled. However, register-based sector protection will still apply. The state of the TBL pin does not affect the state of the Sector Locking Registers. This pin is used as the A4 pin in the A/A Mux interface. 3379C–FLASH–3/05 AT49LH00B4 Interface FWH/LPC A/A Mux Type ...
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... OE The I/O[7:0] pins will be in high-impedance state when the OE pin is deasserted (high). WRITE ENABLE: The WE pin is used in the A/A Mux interface to control write WE operations to the device. AT49LH00B4 6 See “Sector Protection” on page 19. for and ...
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... These field sequences are detailed in the FWH Interface Operation and LPC Interface Operation sections. Since the AT49LH00B4 can be used as either a FWH Flash or an LPC Flash, the device is capa- ble of automatically detecting which type of memory cycle is being performed. For a FWH/LPC cycle, the host will drive the FWH4/LFRAME pin low for one or more clock cycles to initiate the operation. After driving the FWH4/LFRAME pin low, the host will send a START value to indicate 3379C– ...
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... After the IDSEL field has been sent, the 7-clock MADDR (Memory Address) field must be sent to the device to provide the 28-bit starting address location of where to begin read- ing or writing in the memory. Following the MADDR field, the MSIZE (Memory Size) field must be sent to indicate the number of bytes to transfer. AT49LH00B4 8 FWH/LPC Start Fields Cycle Type LPC Cycle – ...
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... MB per FWH memory device, for a total addressable space if 16 FWH memory devices (256 MB each) were used in a system. The AT49LH00B4 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A27 - A23 and A21 - A19. Address bit A22 is used to determine whether reads or writes to the device will be directed to the memory array (A22 = the register space (A22 = 0) ...
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... FWH4/LFRAME FWH/LAD[3:0] 1101b IDSEL A27-A24 A23-A20 A19-A16 START IDSEL AT49LH00B4 10 Valid SYNC Values SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. WSYNC (Wait SYNC) – Device is indicating wait-states (also referred to as short-sync). shows a FWH read cycle that requires three SYNC clocks to access data from the ...
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... YYYY is the most significant nibble of the data byte. The FWH memory device drives the bus to 1111b to indicate a 1111b OUT then float turn-around cycle. The FWH memory device floats its outputs, and the master Float then IN regains control of the bus during this clock cycle. AT49LH00B4 11 ...
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... DATA 13 TAR0 14 TAR1 1111b (float) 15 RSYNC 0000b (ready) 16 TAR0 17 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH00B4 A15-A12 A11-A8 A7-A4 A3-A0 MADDR (1) FWH/LAD[3:0 ] Direction Comments FWH4/LFRAME must be active (low) for the device to respond. ...
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... This is an 8-clock field that is used to provide a 32-bit (A31 - A0) memory address. The 32 address bits allow for the provisioning to access memory space. The AT49LH00B4 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A31 - A24. Address bit A23 is used to determine whether reads or writes to the device will be directed to the memory array (A23 = the register space (A23 = 0) ...
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... Valid values for the SYNC field are shown in Table 7-6. SYNC Value 0000b 0101b AT49LH00B4 14 Valid SYNC Values SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. WSYNC (Wait SYNC) – Device is indicating wait-states (also referred to as short-sync) ...
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... A31-A28 START CYCTYPE + DIR 3379C–FLASH–3/05 shows a LPC read cycle that requires three SYNC clocks to access data from the A27-A24 A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 MADDR AT49LH00B4 1111b High-Z 0101b 0101b 0000b D3-D0 TAR0 TAR1 WSYNC WSYNC RSYNC DATA ...
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... LPC device. After the second clock of the TAR phase, the LPC device assumes con- trol of the bus and drives a “ready” SYNC field to verify that it has received the data. The LPC device will then send a 2-clock TAR field to the master to indicate that it is turning control of the bus back over to the master. AT49LH00B4 16 (1) FWH/LAD[3:0] ...
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... SYNC indicating that the data byte has been received. The LPC memory device drives the bus to 1111b to indicate a 1111b OUT then float turn-around cycle. The LPC memory device floats its outputs, and the master Float then IN regains control of the bus during this clock cycle. AT49LH00B4 A3-A0 ...
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... The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4/LFRAME is driven low for one or more clock cycles after the start of a bus cycle. The memory will place the FWH/LAD[3:0] pins in a high-impedance state, and the AT49LH00B4 18 3379C–FLASH–3/05 ...
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... Table 7-4 and Table 7-8) and no internal Flash operation will be using the FWH/LPC interface and t PHFV AT49LH00B4 time (FWH/LPC and A/A Mux PLPH using the A/A Mux interface) PHAV 19 ...
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... Lock Down status). Reading the Sector Locking Registers, however, will not determine the sta- tus of the TBL and WP pins. When returning from a reset condition or after power-up, the Sector Locking Registers will always default to a state of 01H. AT49LH00B4 20 Hardware Write Protection Options Size (Bytes) ...
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... Sector (Bytes) 10 64K 9 64K 8 64K 7 64K 6 64K 5 64K 4 64K 3 32K 2 16K AT49LH00B4 Register Memory Address FWH MODE LPC MODE Default Value FFBF0002H FF7F0002H FFBE0002H FF7E0002H FFBD0002H FF7D0002H FFBC0002H FF7C0002H FFBB0002H FF7B0002H FFBA0002H FF7A0002H FFB90002H FF790002H FFB88002H FF788002H FFB84002H FF784002H FFB82002H FF782002H ...
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... Lock-Down bit. Table 11-3. Bit 7 Table 11-4. AT49LH00B4 22 Function of Sector Locking Bits Name Description Reserved Reserved for future use. Sector is not read-locked. 0 Normal read operations in the sector can occur. This is the default state ...
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... GPI4 input pin GPI_REG4 1 GPI4 input pin GPI3 input pin GPI_REG3 1 GPI3 input pin GPI2 input pin GPI_REG2 1 GPI2 input pin GPI1 input pin GPI_REG1 1 GPI1 input pin GPI0 input pin GPI_REG0 1 GPI0 input pin AT49LH00B4 LPC Mode Register Type FF7C0100H Read Only . ...
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... The device will then enter standby mode when the FWH4/LFRAME pin is high and no internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high-impedance state. AT49LH00B4 24 FWH Multiple Device Selection ID Strapping Pins ...
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... LPC Multiple Device Selection ID Strapping Pins ID3 ID2 AT49LH00B4 Address Bits ID1 ID0 A22-A19 0 0 1111b 0 1 1110b 1 0 1101b 1 1 1100b 0 0 1011b 0 1 1010b 1 0 1001b 1 1 1000b 0 0 0111b 0 1 0110b 1 0 0101b 1 1 0100b 0 0 0011b 0 1 0010b 1 0 0001b 1 ...
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... FWH or LPC memory write cycle. Therefore, for one “write” device command cycle, 17 FWH/LPC bus cycles are needed. Likewise, for one “read” device command cycle using the FWH/LPC interface, 19 FWH/LPC bus cycles are required. AT49LH00B4 26 A/A Mux Interface Bus Operations ...
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... Sector The Address to Write 40H or 10H be Programmed Write Any Address 70H Write Any Address 50H Write Any Address 90H AT49LH00B4 2nd Command Cycle Type Address Data Read Any Address Data OUT Any Address in Write D0H the Sector Any Address in Write ...
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... Error flags (SR[5,4,1]) in the Status Register can only be set to “1”s by the WSM and can only be reset by the Clear Status Register command. Therefore error is detected, the Status Reg- ister must be cleared before beginning another operation to avoid ambiguity. AT49LH00B4 28 3379C–FLASH–3/05 ...
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... The WSM interrogates the Write-Lock bit, TBL pin pin only after a sector erase or pro- gram operation. Depending on the attempted operation, it informs the system whether or not the selected sector is locked. Product ID Address and Data Address 000000H 000001H AT49LH00B4 Table 16-2 Data 1FH EDH 29 ...
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... Interface) I Program or Erase Current PP Notes: 1. All currents are in RMS unless otherwise noted. These currents are valid for all packages 0 0 AT49LH00B4 30 *NOTICE: (1)(2) + 2.0V for periods <20 ns. CC Test Condition (1) Case Temperature Conditions Voltage range of all inputs FWH4/ LFRAME = ...
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... OUT CC 0.6 V > V > 0 OUT CC 0.18 V > V > OUT V = 0.18 V OUT CC ≤ < ≥ > (1) 0 0.6 V load CC CC (1) 0 0.2 V load 0 OUT OUT AT49LH00B4 Min Max 0 1. -0.5 0.3 V 0. Min Max - -17 OUT Note 2 - -17 OUT Note - 1)/0.015 1)/0.015 Units + 0 ...
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... Minimum and maximum times have different loads. See PCI spec. 2. For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. This parameter applies to any input type (excluding CLK). AT49LH00B4 32 Condition peak-to-peak ...
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... A reset latency of 20 µs will occur if a reset procedure is performed during a programming or erase operation. 3379C–FLASH–3/05 CLK V TEST t VAL FWH/LAD[3:0] (Valid Output Data) FWH/LDA[3:0] (Float Output Data) t OFF CLK t SU Inputs Valid of overdrive over V CC specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production AT49LH00B4 TEST MAX Value 0 ...
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... Notes: 1. Inputs are not “5-volt safe.” 2. Input leakage currents include high-Z output leakage for all bi-directional buffers with high-Z outputs may be higher on the IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions Refer to PCI spec. AT49LH00B4 ...
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... CC (1)(2) ( required from the latter of RDY/BSY or RST going high until addresses are valid. t PLRH t t PLPH PHAV (1)( after the rising edge of R/C without impact on t CHQV GLQV AT49LH00B4 Min Max 100 PHAV Min Max 250 150 50 ...
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... Write Recovery before Read WHGL t Write Recovery before a Valid SRD (Status Register Data) Read WHSV t WE High to RDY/BSY Going Low WHRL Note 0°C to +85° 3.0V to 3.6V AT49LH00B4 36 t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV ...
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... B = Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command 3379C–FLASH–3/ AVCH t t CLAX CHAX t t PHWL WHWL t WLWH t WHDX t DVWH AT49LH00B4 CHWH t WHGL t WHSV Valid SRD t WHRL 37 ...
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... Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP) AT49LH00B4 38 Ordering Code AT49LH00B4-33JC AT49LH00B4-33TC Ordering Code AT49LH00B4-33JX Package Type Package Operation Range 32J Extended Commercial 40T (0° to 85°C) Package Operation Range Extended Commercial 32J (0° ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3379C–FLASH–3/05 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) AT49LH00B4 0.318(0.0125) 0.191(0.0075 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 3.175 – ...
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... E Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LH00B4 40 PIN SEATING PLANE A1 TITLE ...
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