MT47H32M8BP-37V:B Micron Technology Inc, MT47H32M8BP-37V:B Datasheet - Page 25

• Manufacturer Part Number: MT47H32M8BP-37V:B
• Description: IC DDR2 SDRAM 256MBIT 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H32M8BP-37V:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 3.75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10: DDR2 I
Notes: 1–7 apply to the entire table
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
Parameter/Condition
Burst refresh current:
mand at every
HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are floating; Da-
ta bus inputs are floating
Operating bank interleave read current: All
bank interleaving reads, I
(I
t
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are stable during deselects; Data
bus inputs are switching; See I
(page 23) for details
RC =
DD
), AL =
t
RC (I
t
DD
RCD (I
),
t
t
RFC (I
RRD =
DD
DD
) - 1 x
DD
Notes:
t
Specifications and Conditions (Continued)
RRD (I
) interval; CKE is HIGH, CS# is
t
CK =
OUT
t
CK (I
DD
= 0mA; BL = 4, CL = CL
t
DD7
CK (I
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
5. Definitions for I
6. I
7. The following I
DD
),
);
t
tion devices when operated outside of the range 0°C ≤ T
RCD =
Conditions
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
When
T
DD
DD
DD1
DD
t
DD
C
C
CK =
≤ 0°C
≥ 85°C
); REFRESH com-
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
= +1.8V ±0.1V, V
DD4R
t
t
RCD (I
CK (I
, and I
I
ed by 2%; and I
I
ed by 2%; I
30%; and I
T
DD2P
DD0
C
DD
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
DD
IN
IN
< 85°C and the 2X refresh option is still enabled)
),
, I
DD
);
DD
DD7
≤ V
≥ V
and I
DD1
values must be derated (I
conditions:
IL(AC)max
IH(AC)min
require A12 in EMR1 to be enabled during testing.
, I
DDQ
Symbol
DD3P(SLOW)
DD2N
DD6
DD2P
I
REF
I
I
I
DD6L
DD5
DD6
DD7
= +1.8V ±0.1V, V
must be derated by 80% (I
25
, I
= V
DD6
must be derated by 20%; I
DD2Q
Electrical Specifications – I
DDQ
and I
must be derated by 4%; I
, I
/2
Configuration
DD3N
DD7
x4, x8, x16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
x4, x8
x4, x8
, I
must be derated by 7%
x16
x16
256Mb: x4, x8, x16 DDR2 SDRAM
DD3P(FAST)
DDL
DD
= +1.8V ±0.1V, V
limits increase) on IT-option or on AT-op-
, I
DD4R
DD6
DD3P(SLOW)
180
180
250
320
-3
5
3
, I
will increase by this amount if
C
DD4R
DD4W
≤ 85°C:
©2003 Micron Technology, Inc. All rights reserved.
REF
and I
, and I
-37E
must be derated by
170
170
240
300
= V
5
3
DD5W
DD
DD5W
DDQ
Parameters
/2.
must be derat-
must be derat-
C
165
165
230
290
-5E
5
3
≤ +85°C.
Units
mA
mA
mA