MT48LC8M8A2TG-75 L:G Micron Technology Inc, MT48LC8M8A2TG-75 L:G Datasheet - Page 67

IC SDRAM 64MBIT 133MHZ 54TSOP

MT48LC8M8A2TG-75 L:G

Manufacturer Part Number
MT48LC8M8A2TG-75 L:G
Description
IC SDRAM 64MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48LC8M8A2TG-75 L:G

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (8M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 50:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
Single WRITE – With Auto Precharge
t CMH
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
Notes:
t CK
T1
NOP 3
1. For this example, BL = 1.
2. x16: A8, A9 and A11 = “Don’t Care”
3. WRITE command not allowed or
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CL
NOP 3
T2
t CH
T3
NOP 3
ENABLE AUTO PRECHARGE
t CMS
COLUMN m 2
t DS
BANK
WRITE
T4
D
IN
t CMH
t DH
m
67
t WR
t
RAS would be violated.
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T6
NOP
t RP
64Mb: x4, x8, x16 SDRAM
T7
NOP
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
ACTIVE
ROW
ROW
BANK
T8
T9
NOP
DON’T CARE

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