MT48H32M16LFCJ-75:A TR Micron Technology Inc, MT48H32M16LFCJ-75:A TR Datasheet - Page 20

• Manufacturer Part Number: MT48H32M16LFCJ-75:A TR
• Description: IC SDRAM 512MBIT 133MHZ 54VBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H32M16LFCJ-75:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1332-2

NO OPERATION (NOP)
Load Mode Register
ACTIVE
READ
WRITE
PRECHARGE
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
The mode register is loaded via inputs A0–A12, BA0, and BA1. (See "Mode Register" on
page 12.) The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER
commands can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided selects the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided selects the starting
column location. The value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the read burst; if auto precharge is not selected, the row will remain open for subse-
quent accesses. Read data appears on the DQs subject to the logic level on the DQM
inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding
DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will
provide valid data.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided selects the starting
column location. The value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the write burst; if auto precharge is not selected, the row will remain open for subse-
quent accesses. Input data appearing on the DQs is written to the memory array subject
to the DQM input logic level appearing coincident with the data. If a given DQM signal is
registered LOW, the corresponding data will be written to memory; if the DQM signal is
registered HIGH, the corresponding data inputs will be ignored, and a write will not be
executed to that byte/column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
t
RP) after the precharge command is issued. Input A10 determines
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
20
t
MRD is met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Commands