M29F032D70N6T NUMONYX, M29F032D70N6T Datasheet - Page 8

• Manufacturer Part Number: M29F032D70N6T
• Description: IC FLASH 32MBIT 70NS 40TSOP
• Manufacturer: NUMONYX

Specifications of M29F032D70N6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1702-2

M29F032D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
goes High, V
Read and Bus Write operations after t
t
Output section, Table 13 and Figure 12, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
protected Blocks in the memory. Program and
8/36
PLPX
RHEL
. After Reset/Block Temporary Unprotect
, whichever occurs last. See the Ready/Busy
IH
, all other pins are ignored.
IH
, the memory will be ready for Bus
ID
will temporarily unprotect the
IL
, for at least
PHEL
or
Erase operations on all blocks will be possible.
The transition from V
t
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 13 and Figure
12, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
V
power supply for all operations (Read, Program
and Erase).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
V
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
pin to decouple the current surges from the power
supply, see Figure 10, AC Measurement Load Cir-
cuit. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
V
measurements.
PHPHH
CC
LKO
SS
Ground. V
Supply Voltage (5V). V
. This prevents Bus Write operations from ac-
CC
.
Supply Voltage pin and the V
SS
CC3
is the reference for all voltage
IH
OL
.
to V
. Ready/Busy is high-im-
ID
CC
must be slower than
provides
SS
Ground
the
CC