M25P20-VMN6T NUMONYX, M25P20-VMN6T Datasheet - Page 8

• Manufacturer Part Number: M25P20-VMN6T
• Description: IC FLASH 2MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P20-VMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1623-2

M25P20
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P20 features
the following data protection mechanisms:
Table 2. Protected Area Sizes
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.
8/40
BP1 Bit
Status Register
Power On Reset and an internal timer (t
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
–
–
0
0
1
1
Content
Power-up
Write Disable (WRDI) instruction
completion
BP0 Bit
0
1
0
1
none
Upper quarter (Sector 3)
Upper half (two sectors: 2 and 3)
All sectors (four sectors: 0, 1, 2 and 3)
Protected Area
PUW
)
Memory Content
–
–
–
–
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
The Write Protect (W) signal, in co-operation
with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1,
BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the
Hardware Protected Mode (HPM).
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
All sectors
Lower three-quarters (three sectors: 0 to 2)
Lower half (Sectors 0 and 1)
none
1
(four sectors: 0, 1, 2 and 3)
Unprotected Area