M95080-MN6TP STMicroelectronics, M95080-MN6TP Datasheet - Page 20

• Manufacturer Part Number: M95080-MN6TP
• Description: IC EEPROM 8KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95080-MN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 8K (1K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
6.4
20/50
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed write cycle that takes t
Table
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t
reset at the end of the write cycle t
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 and SRWD bits:
●
●
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
Table 6.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in
signal
W
1
0
1
0
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in
The SRWD bit (Status Register Write Disable bit), in accordance with the signal read
on the Write Protect pin (W), allows the user to set or reset the Write protection mode
of the Status Register itself, as defined in
Write Status Register (WRSR) instruction is not executed.
24,
W
, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
SRWD
Table 26
bit
0
0
1
1
Protection modes
Hardware-
Software-
protected
protected
(HPM)
(SPM)
Mode
and
Table
Status Register is
writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Status Register is
Hardware write-protected
The values in the BP1
and BP0 bits cannot be
changed
Write protection of the
W
Table
27).
Doc ID 8028 Rev 10
to complete (as specified in
Status Register
W
W
3.
Write cycle.
.
Figure 10.
Table
Write-protected
Write-protected
6. When in Write-protected mode, the
Protected area
Table
Memory content
21,
(1)
Table
M95160-x, M95080-x
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
22,
Table
Table
23,
3.
(1)