M95080-MN6TP STMicroelectronics, M95080-MN6TP Datasheet - Page 21

• Manufacturer Part Number: M95080-MN6TP
• Description: IC EEPROM 8KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95080-MN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 8K (1K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M95160-x, M95080-x
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases need to be considered, depending on the state of the Write Protect (W) input pin:
●
●
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●
●
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
Table 7.
1. b15 to b11 are Don’t Care on the M95160-x.
Figure 10. Write Status Register (WRSR) sequence
Address bits
b15 to b10 are Don’t Care on the M95080-x.
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction.
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are software-protected (SPM) by the Block
Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against
data modification.
either setting the SRWD bit after driving the Write Protect (W) input pin low
or driving the Write Protect (W) input pin low after setting the SRWD bit
S
C
D
Q
Address range bits
Device
0
1
High Impedance
Doc ID 8028 Rev 10
2
Instruction
(1)
3
4
5
6
M95160-x
A10-A0
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
Table
4
Status
3
2
6.
1
0
M95080-x
AI02282D
A9-A0
Instructions
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