M95640-WMN6P STMicroelectronics, M95640-WMN6P Datasheet - Page 10

• Manufacturer Part Number: M95640-WMN6P
• Description: IC EEPROM 64KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95640-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 8 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 40 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Memory Configuration: 8192 X 8
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8615-5; M95640-WMN6P

Connecting to the SPI bus
3
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Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 3
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
A pull-up resistor connected on each /S input (represented in
device is not selected if the bus master leaves the /S line in the high impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI bus
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this will ensure that S and C do not become high at the
same time, and so, that the t
CS3
SPI interface with
(CPOL, CPHA) =
SPI bus master
(0, 0) or (1, 1)
CS2
shows three devices, connected to an MCU, on a SPI bus. Only one device is
Bus master and memory devices on the SPI bus
CS1
SDO
SDI
SCK
R
R
SHCH
Doc ID 16877 Rev 15
C Q D
S
SPI memory
device
requirement is met. The typical value of R is 100 k .
W
V
CC
HOLD
V
SS
M95640, M95640-W, M95640-R, M95640-DR
R
C Q D
S
SPI memory
device
W
Figure
V
HOLD
CC
V
SS
R
3) ensures that each
C Q D
S
SPI memory
device
W
V
CC
HOLD
AI12836b
V
SS
V
V
CC
SS