M95640-WMN6P STMicroelectronics, M95640-WMN6P Datasheet - Page 26

• Manufacturer Part Number: M95640-WMN6P
• Description: IC EEPROM 64KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95640-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 8 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 40 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Memory Configuration: 8192 X 8
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8615-5; M95640-WMN6P

Instructions
6.8
6.9
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Write Identification Page
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. Writing this page is achieved with the Write
Identification Page instruction (see
bits of the instruction byte, address byte, and at least one data byte are then shifted in on
Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A5] are
Don't Care, the [A4:A0] address bits define the byte address inside the identification page.
Figure 15. Write Identification Page sequence
Read Lock Status
The Read Lock Status instruction is used to read the lock status. To send this instruction to
the device, Chip Select (S) first has to be driven low. The bits of the instruction byte and
address bytes are then shifted in on Serial Data input (D). Address bit A10 must be 1, all
other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte
read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the lock is
not active. If Chip Select (S) continues to be driven low, the same data byte is shifted out.
The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is
shown in
Figure
16.
Doc ID 16877 Rev 15
Table
4), the Chip Select signal (S) is first driven low. The
M95640, M95640-W, M95640-R, M95640-DR