M95640-WMN6P STMicroelectronics, M95640-WMN6P Datasheet - Page 32

• Manufacturer Part Number: M95640-WMN6P
• Description: IC EEPROM 64KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95640-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 8 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 40 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Memory Configuration: 8192 X 8
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8615-5; M95640-WMN6P

DC and AC parameters
Table 19.
1. These timings are offered with grade3 devices referenced with “/PC” process letters only (see the last digits in the
2. t
3. Value guaranteed by characterization, not 100% tested in production.
4. t
32/44
Symbol
t
t
t
t
t
t
t
SHQZ
QLQH
QHQL
CLCH
CHCL
CLQV
HLQZ
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SHCH
CHSH
CHDX
HHCH
HHQV
SLCH
CHSL
CH
DVCH
HLCH
CLHH
CLQX
numbering).
equal to (or greater than) t
SHSL
CLHL
CL
CH
CLQV
t
f
W
C
(2)
(2)
+ t
(3)
(3)
(3)
(4)
(3)
(3)
(3)
must be compatible with t
CL
must never be lower than the shortest possible clock period, 1/f
t
t
t
t
f
t
CSS1
CSS2
t
Alt.
t
t
t
t
SCK
t
CSH
t
DSU
t
t
CLH
t
t
AC characteristics (M95320-W, device grade 3)
CLL
t
DIS
WC
HO
RO
CS
RC
FC
DH
t
FO
HZ
LZ
V
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output valid
HOLD low to output high-Z
Write time
CLQV
; in all other cases, t
Test conditions specified in
CL
(clock low time): if the SPI bus master offers a Read setup time t
Parameter
Doc ID 5711 Rev 12
CL
must be equal to (or greater than) t
Table 9
C
(max).
Min.
2.5 V to 5.5 V
D.C.
100
and
90
90
90
90
90
90
20
30
70
40
0
0
0
Table 11
Max.
M95320, M95320-W, M95320-R
100
100
60
50
50
50
5
1
1
5
CLQV
+t
3.0 V to 5.5 V
SU
Min.
D.C.
30
30
40
30
30
42
40
10
10
30
30
0
0
0
.
SU
= 0 ns, t
Max.
10
40
40
40
40
40
40
2
2
5
CL
(1)
can be
Part
Unit
MHz
ms
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns