W9725G6IB-25 Winbond Electronics, W9725G6IB-25 Datasheet
W9725G6IB-25
Specifications of W9725G6IB-25
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W9725G6IB-25 Summary of contents
Page 1
... Self Refresh Entry Command ..........................................................................................21 7.3.8 Self Refresh Exit Command .............................................................................................22 7.3.9 Refresh Command ...........................................................................................................22 7.3.10 No-Operation Command ..................................................................................................23 7.3.11 Device Deselect Command..............................................................................................23 7.4 Read and Write access modes ...........................................................................................................23 7.4.1 Posted CAS 7.4.1.1 Examples of posted ....................................................................................................................23 operation......................................................................23 CAS - 1 - W9725G6IB Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... AC Overshoot / Undershoot Specification ...........................................................................................64 9.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: ........................64 9.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins:..........64 10. TIMING WAVEFORMS .......................................................................................................................65 10.1 Command Input Timing.......................................................................................................................65 10.2 Timing of the CLK Signals...................................................................................................................65 W9725G6IB Publication Release Date: Oct. 23, 2009 - 2 - Revision A04 ...
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... Active Power Down Mode Entry and Exit Timing.......................................................................81 10.31 Precharged Power Down Mode Entry and Exit Timing ..............................................................81 10.32 Clock frequency change in precharge Power Down mode ........................................................82 11. PACKAGE SPECIFICATION ..............................................................................................................83 Package Outline WBGA-84 (8x12.5 mm 12. REVISION HISTORY ..........................................................................................................................84 2 ).......................................................................................................83 Publication Release Date: Oct. 23, 2009 - 3 - W9725G6IB Revision A04 ...
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... GENERAL DESCRIPTION The W9725G6IB is a 256M bits DDR2 SDRAM, organized as 4,194,304 words × 4 banks × 16 bits. This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general applications. W9725G6IB is sorted into two speed grades: -25 and -3. The -25 is compliant to the DDR2-800 (6-6-6) specification, the -3 is compliant to the DDR2-667 (5-5-5) specification. ...
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... Self refresh current DD6 I Operating bank interleave read current DD7 SPEED GRADE Bin(CL-tRCD-tRP) Min. @ Max. Min. @ Max. Min. @ Max. Min. @ Max. Min. Min. Min. Min. Max. Max. Max. Max. Max. Max. Max W9725G6IB DDR2-800 DDR2-667 6-6-6 5-5-5 -25 -3 − 2.5 nS − 3. ...
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... VDDQ D DQ10 E VSSQ LDQS F LDQS G VDDQ H DQ2 J VSSDL K RAS L CAS A11 R NC Publication Release Date: Oct. 23, 2009 - 6 - W9725G6IB 8 9 UDQS VDDQ VSSQ DQ15 DQ8 VDDQ VSSQ DQ13 VDDQ VSSQ DQ7 DQ0 VDDQ VSSQ DQ5 CLK VDD CLK ODT CS A0 VDD A4 A8 ...
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... DQ Power Supply: 1.8V ± 0.1V. DQ Power Supply DQ Ground DQ Ground. Isolated on the device for improved noise immunity. No Connection No connection. DLL Ground DLL Ground. DLL Power Supply: 1.8V ± 0.1V. DLL Power Supply - 7 - W9725G6IB DESCRIPTION are masked when CS is Publication Release Date: Oct. 23, 2009 Revision A04 registered ...
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... CELL ARRAY BANK #0 SENSE AMPLIFIER SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER SENSE AMPLIFIER Publication Release Date: Oct. 23, 2009 - 8 - W9725G6IB CELL ARRAY BANK #1 ODT DQ0 | DQ DQ15 ODT BUFFER LDQS LDQS CONTROL UDQS UDQS ...
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... The DDR2 SDRAM is now ready for normal operation. DDQ voltage ramp are driven from a single power converter output DDQ W9725G6IB *1 and ODT at a LOW state (all other ramps from 300 DD | ≦ 0.3 volts. DDQ during voltage ramp time to avoid DDQ ≧ V ≧ ...
Page 10
... DD min is achieved when PRE MRS REF REF ALL MRD RP RFC MRD DLL min 200 Cycle Reset - 10 - W9725G6IB ramps from 300 min. DD min is achieved on V must be no DDQ DDQ t IS ANY MRS EMRS EMRS CMD RFC MRD Follow OCD OIT Flow chart ...
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... ODT setting. A10 DLL TM CAS Latency A7 Mode 0 Normal 1 Test Write recovery for Auto-precharge A11 A10 Reserved Reserved Reserved Figure 2—Mode Register Set (MRS W9725G6IB Address Field BT Burst Length Mode Register Burst Length A3 Burst Type Sequential Interleave CAS Latency Latency Reserved Reserved Reserved ...
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... Output Driver Impedance Control Strobe Function Matrix Output driver A1 impedance control DQS DQS 0 DQS DQS DQS Hi-z 1 Reduced Figure 3—EMR ( W9725G6IB Address Field BT Rtt O.I.C DLL Extended Mode Register (1) A0 DLL Enable 0 Enable 1 Disable Additive Latency A4 A3 Latency ...
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... Self Refresh rate must be enabled by setting bit A7 to "1" before the Self Refresh mode can be entered SELF A7 High Temperature Self Refresh Rate Enable 0 Disable 1 Enable (Optional) Figure 4—EMR ( W9725G6IB ) must be satisfied to MRD Address Field 1 0* Extended Mode Register (2) Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... EMR (3) must be programmed during initialization for proper operation Note: 1. All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR (3 Figure 5—EMR (3) Publication Release Date: Oct. 23, 2009 - 14 - W9725G6IB Revision A04 ...
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... ALL OK EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Publication Release Date: Oct. 23, 2009 - 15 - W9725G6IB EMRS: Drive(0) DQ &DQS Low; DQS High Test Need Calibration EMRS: Enter Adjust Mode BL=4 code input to all DQs ...
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... NOP 1 Increase by 1 step 0 Decrease by 1 step 1 Increase by 1 step 0 Decrease by 1 step - 16 - W9725G6IB at bit time 1, and so forth. The driver Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step ...
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... DT1 DT2 DT3 OCD calibration mode exit Figure 7—OCD Adjust Mode after “enter drive mode” command and all OIT after “OCD calibration mode exit” command as shown in Figure 8. Figure 8—OCD Drive Mode - 17 - W9725G6IB /t should be met fixed order and is not affected T3 NOP ...
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... Rval1 Rval2 Rval3 Input Pin Rval1 Rval2 Rval3 sw2 sw1 sw3 SSQ SSQ SSQ MOD window for proper operation. The timings are shown MOD Publication Release Date: Oct. 23, 2009 - 18 - W9725G6IB ,min and t ,max, and CKE MOD Revision A04 ...
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... Figure 11—ODT update delay timing - t MOD window, until t MOD EMRS NOP NOP t MOD,max , as measured from outside MOD Publication Release Date: Oct. 23, 2009 - 19 - W9725G6IB ,max is met. MOD NOP NOP NOP AOND New setting Revision A04 ...
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... A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected, the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not selected, the row will remain open for subsequent accesses. RAS ). The minimum time interval between Bank Activate commands RCD - 20 - W9725G6IB and t , respectively. The minimum RRD CCD Publication Release Date: Oct ...
Page 21
... Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. min) and t (min) are satisfied. RAS( RTP Publication Release Date: Oct. 23, 2009 - 21 - W9725G6IB Revision A04 ...
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... CKE ≧ tRP CMD Precharge NOP . XSRD t . REFI (max.) . REFI ≧ tRFC REF REF NOP Figure 13—Refresh command - 22 - W9725G6IB for proper operation XSRD ). NOP or Deselect RFC XSNR RFC ≧ tRFC NOP ANY Publication Release Date: Oct. 23, 2009 Revision A04 XSNR . ). ...
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... Chapter 10) 7.4.1.1 Examples of posted Examples of a read followed by a write to the same bank where and where are shown in Figures 14 and 15, respectively. operation CAS - 23 - W9725G6IB * . The page , and is a minimum of 2 clocks for CCD RCDmin Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... Burst read and write interrupt timing diagram in Chapter 10 Write A-Bank WL=RL-1=4 CL=3 RL=AL+CL=5 Dout0 Dout1 Dout2 Dout3 AL=0 Read Write A-Bank A-Bank CL=3 RL=AL+CL=3 Dout0 Dout1 Dout2 Dout3 Publication Release Date: Oct. 23, 2009 - 24 - W9725G6IB Din1 Din2 Din3 Din0 WL=RL-1=2 Din0 Din1 Din2 Din3 Revision A04 ...
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... The time from the completion of the burst write to bank precharge is the write recovery time (WR). (Example timing waveforms refer to 10.9 and 10.10 Data input (write) timing and Burst write operation diagram in Chapter 10) Sequential Addressing Interleave Addressing (decimal Publication Release Date: Oct. 23, 2009 - 25 - W9725G6IB (decimal Revision A04 ...
Page 26
... Minimum Write to Precharge timing BL clock after the un-interrupted burst end and not from the end of the actual burst end. (Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10) W9725G6IB , where Publication Release Date: Oct. 23, 2009 ...
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... BA1 BA0 LOW LOW LOW HIGH HIGH LOW HIGH HIGH Don’t Care Don’t Care is satisfied. RAS - 27 - W9725G6IB Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All Banks ). A precharge referenced WR Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... Auto-precharge RP ) from the previous bank activation has been satisfied. Limit) and (t Limit) diagram in Chapter 10 has been satisfied from the previous bank activation has been satisfied W9725G6IB (min) are satisfied. (Example timing ends (not at the RTP + (Example timing RP CK(avg ...
Page 29
... Minimum Delay between “From Command” to “To Command” BL/2 + max(RTP BL/2 + max(RTP BL/2 + max(RTP BL/2 + max(RTP RFC Publication Release Date: Oct. 23, 2009 - 29 - W9725G6IB Unit Notes clks 1, 2 clks 1, 2 clks 1, 2 clks 1, 2 clks 2 WR clks 2 WR clks ...
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... Clock frequency change in precharge Power Down mode diagram in Chapter 10) has been satisfied. Maximum power down duration is limited by CKE has been satisfied. A valid, executable CKE , t XP XARD - 30 - W9725G6IB if maximum posting of tREFI , after CKE goes HIGH. XARDS Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 7.9. BA1 A12 A10 A9-A0 BA0 A11 BA Row Address Column L Column BA Column H Column BA Column L Column BA Column H Column BA OP Code Publication Release Date: Oct. 23, 2009 - 31 - W9725G6IB NOTES CS RAS CAS 1 1 1,2 1,2 1,2 1,2 1 1,4 ...
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... Refer to the Command Truth Table (200 clocks) is satisfied. XSRD + )” in Self Refresh and Power Down. However ODT must be driven REF W9725G6IB 3 ACTION (N) NOTES Maintain Power Down 11, 13, 15 Power Down Exit 4, 8, 11, 13 Maintain Power Down 11, 15, 16 Self Refresh Exit Active Power Down 4, 8, 10, 11, Entry ...
Page 33
... BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 33 - W9725G6IB ACTION NOTES NOP or Power down NOP or Power down ILLEGAL ILLEGAL Row activating Precharge/ Precharge all banks Auto Refresh or Self Refresh Mode/Extended register accessing NOP NOP Begin read Begin write ...
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... BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA L H BA, RA ACT L BA, A10 PRE/PREA X AREF/SELF H L Op-Code MRS/EMRS - 34 - W9725G6IB ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> ...
Page 35
... READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 35 - W9725G6IB ACTION NOTES NOP-> Bank active after t WR NOP-> Bank active after t WR ILLEGAL New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Precharge after t WR NOP-> Precharge after t WR ...
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... WRITA Writing Reading with with Auto-precharge PRE, PREA PRE, PREA PRE, PREA Precharging - 36 - W9725G6IB CKEL Refreshing CKEL CKEL Autoomatic Sequence Command Sequence Read CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down CKEH = CKE HIGH, exit Self Refresh ...
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... V 0 DDQ V - 0.04 V REF REF of the transmitting device and V is expected to track variations in V REF (dc). REF of receiving device. REF . AC parameters are measured with W9725G6IB RATING UNIT NOTES -1.0 ~ 2.3 V -0.5 ~ 2.3 V -0.5 ~ 2.3 V -0.5 ~ 2.3 V °C -55 ~ 100 RATING UNIT NOTES ° MAX ...
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... V ) – 100% Δ DDQ = 1.8V ± 0.1V) DDQ MIN 0.125 REF -0.3 = 1.8V ± 0.1V) DDQ MIN 0.200 REF 1 V – V SSQ PEAK - 38 - W9725G6IB NOM. MAX. UNIT NOTES Ω 150 180 1 Ω Ω and I(V IH (ac) – I(V ) ILac) MAX. ...
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... TT − -13.4 13 )/I must be less than 21 Ω for values of V DDQ OH /I must be less than 21 Ω for values max minus a noise margin are delivered to an SSTL_18 receiver W9725G6IB MIN. MAX. UNIT 1.0 2.0 pF − 0.25 pF 1.0 1.75 pF − 0.25 pF 2.5 3 ...
Page 40
... Data bus inputs are SWITCHING. −25 MAX RAS RASmin(IDD) 100 , RAS RASmin(IDD) RCD 110 Fast PDN Exit 36 MRS(12 Slow PDN Exit 10 MRS(12 RP(IDD) 75 Publication Release Date: Oct. 23, 2009 - 40 - W9725G6IB −3 UNIT NOTES MAX 1,2,3,4,5,6 100 mA 1,2,3,4,5 1,2,3,4,5 1,2,3,4,5 1,2,3,4,5 1,2,3,4,5 1,2,3,4,5,6 Revision A04 ...
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... HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes mA; OUT , RP(IDD RP(IDD) interval; RFC(IDD) = 0mA; OUT - RCD(IDD) CK(IDD RRD RRD(IDD) RCD 0.1V W9725G6IB 155 135 mA 1,2,3,4,5,6 170 150 mA 1,2,3,4,5,6 145 135 mA 1,2,3,4,5 1,2,3,4,5,6 195 170 mA 1,2,3,4,5,6 Publication Release Date: Oct. 23, 2009 Revision A04 ...
Page 42
... IDD Measurement Test Parameters SPEED GRADE Bin(CL-t -t RCD RP) CL (IDD) t CK(IDD) t RCD(IDD) t RP(IDD) t RC(IDD) t RASmin(IDD) t RASmax(IDD) t RRD(IDD)-1KB t FAW(IDD)-1KB t RFC(IDD) DDR2-800 DDR2-667 (-25) (-3) 6-6-6 5-5 2 70000 70000 7.5 7 W9725G6IB UNIT tCK Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... RP − 7.5 − 7.5 − 175 − 250 375 − 375 − − 0.6 -0.25 0.25 − 0.2 − 0.2 − 0.35 − 0. W9725G6IB DDR2-667 (-3) 25 5-5-5 UNITS NOTES MIN. MAX. − − nS − 70000 nS 4,23 − − 7.8 μS − ...
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... AC,min + 2 AC,min + AC,max 1 3 − − CK(avg) IS CK(avg) − Publication Release Date: Oct. 23, 2009 - 44 - W9725G6IB 25 UNITS NOTES MAX. − t CK(avg) 0 CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 − t CK(avg) ...
Page 45
... Logic levels V levels REF t IS(ref) Figure 17 — Differential input waveform timing – tIS and tIH VTT = VDDQ/2 25Ω IH(base) IS(base) IH(base IH(ref) IS(ref) IH(ref W9725G6IB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 tDS/tDH derating with differential data strobe (page 58). VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - tLZ,tRPRE begin point = Publication Release Date: Oct. 23, 2009 - 46 - W9725G6IB Revision A04 ...
Page 47
... That is, these parameters should be met whether clock jitter is present or not DH(base) DH(base) DS(base DH(ref) DS(ref) DH(ref W9725G6IB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V ...
Page 48
... That is, these parameters should be met whether clock jitter is present or not. 29. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U)DQS/ DQS ) crossing. W9725G6IB Publication Release Date: Oct. 23, 2009 - 48 - ...
Page 49
... N = 200 ⎡ ⎤ N ∑ tCL / (N × tCK(avg)) ⎢ ⎥ j ⎣ ⎦ where N = 200 Publication Release Date: Oct. 23, 2009 - 49 - W9725G6IB DDR2-800 UNIT MIN. MAX. -100 100 pS - -200 200 pS -160 160 pS -150 150 pS -175 175 pS -200 200 pS -200 200 ...
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... R(2per) ⎢ for tER R(3per) ⎢ ⎢ for tER R(4per) ⎢ for tER R(5per) ⎢ ⎢ ≤ ≤ for tER R(6 – 10per) ⎢ ≤ ≤ ⎢ for tER R(11 – ⎣ Publication Release Date: Oct. 23, 2009 - 50 - W9725G6IB 50per) Revision A04 ...
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... Publication Release Date: Oct. 23, 2009 - 51 - W9725G6IB MAX UNIT pS pS tJIT(duty),max pS tJIT(duty),max Revision A04 ...
Page 52
... Timings are specified with DQs and DM input slew rate of 1.0V/nS. 42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/nS in differential strobe mode. W9725G6IB Publication Release Date: Oct. 23, 2009 - 52 - ...
Page 53
... W9725G6IB 1.0 V/nS Unit ΔtIS ΔtIH +210 +154 pS +203 +149 pS +193 +143 pS +180 +135 pS +160 +105 pS +127 +81 pS +60 +60 pS +55 +46 pS +47 +29 ...
Page 54
... IL(dc) V max IL(ac Δ REF(dc) Setup Slew Rate = Falling Signal TF Δ Figure 20 —Illustration of nominal slew rate for nominal slew rate TR Δ Setup Slew Rate IL(ac)max = Rising Signal Publication Release Date: Oct. 23, 2009 - 54 - W9725G6IB REF region IH(ac)min REF(dc) TR Δ IS Revision A04 ...
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... Setup Slew Rate Falling Signal = Figure 21 —Illustration of tangent line for nominal line tangent tangent line TR Δ tangent line[V Setup Slew Rate Rising Signal = - V ] REF(dc) IL(ac)max TF Δ Publication Release Date: Oct. 23, 2009 - 55 - W9725G6IB t IH line REF region - V ] IH(ac)min REF(dc) TR Δ IS Revision A04 ...
Page 56
... IL(dc) V max IL(ac Hold Slew Rate REF(dc) Rising Signal = TR Δ Figure 22 —Illustration of nominal slew rate for nominal slew rate Δ Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Oct. 23, 2009 - 56 - W9725G6IB t IH REF region TF Δ IH(dc)min REF(dc) TF Δ IH Revision A04 ...
Page 57
... Rising Signal Figure 23 —Illustration of tangent line for tangent tangent line nominal line TR Δ REF(dc) IL(ac)max TR Δ tangent line[V Hold Slew Rate Falling Signal = Publication Release Date: Oct. 23, 2009 - 57 - W9725G6IB t IH nominal line line REF region TF Δ IH(dc)min REF(dc) TF Δ IH Revision A04 ...
Page 58
... These values are typically not subject to production test. They are verified by design and characterization. DQS/ DQS Differential Slew Rate 1.8 V/nS 1.6 V/nS 1 - -10 - - Publication Release Date: Oct. 23, 2009 - 58 - W9725G6IB 1.2 V/nS 1.0 V/nS 0 -47 14 -35 26 -23 38 -89 -12 - -52 -140 -40 -128 -28 -116 Revision A04 - ...
Page 59
... Figure 24 —Illustration of nominal slew rate for tDS (differential DQS, DQS ) W9725G6IB Publication Release Date: Oct. 23, 2009 - 59 - Revision A04 ...
Page 60
... Figure 25 —Illustration of tangent line for tDS (differential DQS, DQS ) W9725G6IB Publication Release Date: Oct. 23, 2009 - 60 - Revision A04 ...
Page 61
... Figure 26 —Illustration of nominal slew rate for tDH (differential DQS, DQS ) W9725G6IB Publication Release Date: Oct. 23, 2009 - 61 - Revision A04 ...
Page 62
... Figure 27 —Illustration tangent line for tDH (differential DQS, DQS ) W9725G6IB Publication Release Date: Oct. 23, 2009 - 62 - Revision A04 ...
Page 63
... VDDQ - 0.125 OX (ac) V DDQ V min IH(ac) V min IH(dc) V REF V max IL(dc) V max IL(ac △TR V min - V IH(ac) REF Rising Slew = △ W9725G6IB VALUE UNIT 0 DDQ 1.0 V 1.0 V/nS MAX. UNIT VDDQ + 0.6 V 0.5 x VDDQ + 0.175 V 0.5 x VDDQ + 0.125 V V DDQ V TR Crossing point ...
Page 64
... SS −25 0.5 0.5 0.23 0.23 SSQ Maximum Amplitude DDQ /V SS SSQ Maximum Amplitude Time (nS W9725G6IB −3 UNIT 0.5 V 0.5 V 0.8 V-nS 0.8 V-nS −3 UNIT 0.5 V 0.5 V 0.23 V-nS 0.23 V-nS Overshoot Area Undershoot Area Publication Release Date: Oct. 23, 2009 ...
Page 65
... TIMING WAVEFORMS 10.1 Command Input Timing CLK CLK CS RAS CAS WE A0~A12 BA0,1 10.2 Timing of the CLK Signals CLK CLK CLK CLK Refer to the Command Truth Table Publication Release Date: Oct. 23, 2009 - 65 - W9725G6IB IH(AC) V IL(AC Revision A04 ...
Page 66
... ODT Timing for Active/Standby Mode 10.4 ODT Timing for Power Down Mode W9725G6IB Publication Release Date: Oct. 23, 2009 - 66 - Revision A04 ...
Page 67
... AOFD IL(ac AOFPD(max AOND IH(ac) t AONPD(max) Publication Release Date: Oct. 23, 2009 - 67 - W9725G6IB Active & Standby mode timings to be applied Power Down mode timings to be applied TT Active & Standby mode timings to be applied R TT Power Down mode timings to be applied R TT Revision A04 ...
Page 68
... T7 t AXPD t IS ODT V IL(ac) Internal Term Res ODT V IL(ac) Internal R TT Term Res IH(ac) ODT Internal Term Res IH(ac) ODT Internal Term Res. t AONPD(max) Publication Release Date: Oct. 23, 2009 - 68 - W9725G6IB T8 T9 T10 AOFD t AOFPD(max) R RTT TT t AOND R TT Revision A04 ...
Page 69
... Burst read operation: RL=5 (AL=2, CL=3, BL= CLK/CLK Posted CAS CMD NOP NOP READ A DQS, DQS DQ DQSmax NOP NOP NOP NOP NOP NOP NOP NOP W9725G6IB t RPST DQSmax NOP NOP NOP NOP NOP NOP t DQSCK Dout Dout Dout Dout Publication Release Date: Oct. 23, 2009 Revision A04 ...
Page 70
... DQS DQS DQs NOP NOP NOP NOP t t DQSS DQSS t DSS DIN DIN DIN DQSS DQSS t t DSH DSH DIN DIN DIN W9725G6IB NOP NOP Precharge Completion of The Burst Write t DSS t WR DIN DIN A3 Publication Release Date: Oct. 23, 2009 Revision A04 ...
Page 71
... The seamless burst write operation is supported by enabling a write command every other clock for operation, every four clocks for operation. This operation is allowed regardless of same or different banks as long as the banks are activated NOP NOP NOP DOUT NOP NOP NOP DOUT DOUT DOUT W9725G6IB NOP NOP NOP DOUT DOUT DOUT DOUT DOUT DOUT NOP NOP NOP ...
Page 72
... NOP READ A DQS, DQS DQ's 10.14 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL= NOP NOP NOP READ B Dout Dout Dout Dout Dout W9725G6IB NOP NOP NOP Dout Dout Dout Dout Dout Dout Dout Publication Release Date: Oct. 23, 2009 Revision A04 ...
Page 73
... Write operation with Data Mask: WL=3, AL=0, BL=4) Data Mask Timing DQS/ DQS DQ DM CLK CLK Write CMDMAND Case 1: min t DQSS DQS/DQS DQ DM Case 2: max t DQSS DQS/DQS IH(ac) IH(ac IH(dc) IH(dc IH(dc) IL(dc IL(ac) IL(ac DQSS (min DQSS (max W9725G6IB t WR Publication Release Date: Oct. 23, 2009 Revision A04 ...
Page 74
... Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, t ≦2clks) 10.17 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, t ≦2clks) W9725G6IB Publication Release Date: Oct. 23, 2009 - 74 - RTP RTP Revision A04 ...
Page 75
... Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, t ≦2clks CLK/CLK Post CAS CMD NOP READA AL + BL/2 clks DQS, DQS DQ NOP NOP Precharge RAS ≧ t RTP - 75 - W9725G6IB Bank A NOP NOP NOP Activate t RP Dout Dout Dout Dout Publication Release Date: Oct. 23, 2009 Revision A04 RTP RTP ...
Page 76
... Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, t >2clks) RTP 10.21 Burst write operation followed by precharge (RL- CLK/CLK Post CAS NOP CMD WRITE A DQS, DQS DQ NOP NOP NOP DIN DIN DIN DIN W9725G6IB NOP NOP NOP Precharge Completion of the Burst Write t WR Publication Release Date: Oct. 23, 2009 Revision A04 ...
Page 77
... DQS, DQS DQ's first 4-bit prefetch second 4-bit prefetch NOP NOP NOP NOP Dout Dout RTP t RTP Precharge begins here - 77 - W9725G6IB RTP Bank A NOP NOP Activate t RP Dout Dout Dout Dout Dout Dout Publication Release Date: Oct. 23, 2009 Revision A04 ≦ ...
Page 78
... Burst read with Auto-precharge followed by an activation to the same bank (t Limit): RL=5 (AL=2, CL=3, internal NOP NOP NOP + t RTP Dout Dout RTP Precharge begins here =3, BL=4, t RCD - 78 - W9725G6IB Bank A NOP NOP Activate Dout Dout ≦2clks) RTP Publication Release Date: Oct. 23, 2009 Revision A04 NOP ...
Page 79
... WRA Bank A A10 = 1 DQS, DQS WL= RL DQ's =3, BL=4, t RCD Limit): WL=2, WR=2, BL= NOP NOP NOP Completion of the Burst Write DIN DIN DIN DIN W9725G6IB ≦2clks) RTP = Bank A NOP NOP NOP Activate Auto-precharge Begins min. Publication Release Date: Oct. 23, 2009 Revision A04 ...
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... Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 10.29 Self Refresh Timing W9725G6IB Publication Release Date: Oct. 23, 2009 - 80 - Revision A04 ...
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... Active Power Down Mode Entry and Exit Timing 10.31 Precharged Power Down Mode Entry and Exit Timing W9725G6IB Publication Release Date: Oct. 23, 2009 - 81 - Revision A04 ...
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... X+1 Y Y+2 Y+1 NOP t Frequency change IS Occurs here Stable new clock before power down exit Publication Release Date: Oct. 23, 2009 - 82 - W9725G6IB Y+3 Y+4 z DLL NOP NOP Valid RESET 200 Clocks ODT is off during DLL RESET Revision A04 ...
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... BSC. 6.40 BSC. 0.80 BSC. 0.80 BSC. Note: 1. Ball land : 0.5mm --- 0.15 --- 0.20 0.10 --- - 83 - W9725G6IB aaa E B Ball Land Ball Opening 2. Ball opening : 0.4mm 3. PCB Ball land suggested 0.4mm Publication Release Date: Oct. 23, 2009 Revision A04 C 4X ...
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... IS IH Add DQ and DM input setup/hold time parameters 44, 46~ (ref Revise Rtt=50 ohm notes description in section 7.2.2.1 12, 38 EMRS (1) and 9.4 ODT DC Characteristics 83 Revise WBGA-84 package dimension drawing Important Notice - 84 - W9725G6IB DESCRIPTION Publication Release Date: Oct. 23, 2009 Revision A04 ...