DP8422AV-20 National Semiconductor, DP8422AV-20 Datasheet - Page 33

• Manufacturer Part Number: DP8422AV-20
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-20

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-20

7 0 RAS and CAS Configuration Modes
7 2 MEMORY INTERLEAVING
Memory interleaving allows the cycle time of DRAMs to be
reduced by having sequential accesses to different memory
banks Since the DP8420A 21A 22A have separate pre-
charge counters per bank sequential accesses will not be
delayed if the accessed banks use different RAS outputs
To ensure different RAS outputs will be used a mode is
selected where either one or two RAS outputs will be as-
serted during an access The bank select or selects B0 and
B1 are then tied to the least significant address bits caus-
ing a different group of RASs to assert during each sequen-
tial access as shown in Figure 27 In this figure there should
be at least one clock period of all RAS’s negated between
different RAS’s being asserted to avoid the condition of a
CAS before RAS refresh cycle
FIGURE 27 Memory Interleaving (C6 C5 C4
33
(Continued)
7 3 ADDRESS PIPELINING
Address pipelining allows several access RASs to be as-
serted at once Because RASs can overlap each bank re-
quires either a mode where one RAS and one CAS are used
per bank as shown in Figure 28a or where two RASs and
two CASs are used per bank as shown in Figure 28b Byte
writing can be accomplished in a 16-bit word system if two
RASs and two CASs are used per bank In other systems
WEs (or external gating on the CAS outputs) must be used
to perform byte writing If WEs are used separate data in
and data out buffers must be used If the array is not layed
out this way a CAS to a bank can be low before RAS which
will cause a refresh of the DRAM not an access To take
full advantage of address pipelining memory interleaving is
used To memory interleave the least significant address
bits should be tied to the bank select inputs to ensure that
all ‘‘back to back’’ sequential accesses are not delayed
since different memory banks are accessed
e
1 1 0 during Programming)
TL F 8588 – D3