DP8421AV-25 National Semiconductor, DP8421AV-25 Datasheet - Page 12

• Manufacturer Part Number: DP8421AV-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421AV-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421AV-25

3 0 Programming and Resetting
3 3 PROGRAMMING BIT DEFINITIONS (Continued)
Symbol
R5 R4
0 0
0 1
1 0
1 1
R3 R2
0 0
0 1
1 0
1 1
R1 R0
0 0
0 1
1 0
1 1
WAIT DTACK during Burst (See Section 5 1 2 or 5 2 2)
NO WAIT STATES If R7
If R7
1T If R7
WAIT will negate from the positive edge of CLK after the ECASs have been asserted
If R7
DTACK will assert from the positive edge of CLK after the ECASs have been asserted
WAIT will negate on the negative level of CLK after the ECASs have been asserted
If R7
DTACK will assert from the negative level of CLK after the ECASs have been asserted
0T If R7
the ECAS inputs are asserted
If R7
the ECAS inputs are asserted
WAIT DTACK Delay Times (See Section 5 1 1 or 5 2 1)
NO WAIT STATES If R7
will negate when RAS is negated during delayed accesses
NO WAIT STATES If R7
1T If R7
NO WAIT STATES
WAIT will negate on the negative level of CLK after the access RAS during delayed accesses
1T If R7
1 T If R7
of CLK after the access RAS
RAS Low and RAS Precharge Time
RAS asserted during refresh
RAS precharge time
RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422A)
RAS asserted during refresh
RAS precharge time
RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422A)
RAS asserted during refresh
RAS precharge time
RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422A)
RAS asserted during refresh
RAS precharge time
RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422A)
T If R7
T If R7
T If R7
e
e
e
e
1 programming DTACK will remain asserted during burst portion of access
1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted
1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted
1 during programming DTACK will negate when the ECAS inputs are negated DTACK will assert when
e
e
e
e
e
e
e
e
0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted
0 during programming WAIT will assert when the ECAS inputs are negated WAIT will negate when
1 during programming DTACK will be asserted on the positive edge of CLK after the access RAS
0 during programming WAIT will negate on the positive edge of CLK after the access RAS
0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted
0 during programming WAIT will negate on the negative level of CLK after the access RAS
1 during programming DTACK will be asserted on the negative level of CLK after the access RAS
1 during programming DTACK will be asserted on the negative level of CLK after the positive edge
e
e
e
e
T If R7
1 positive edge of CLK
2 positive edges of CLK
2 positive edges of CLK
3 positive edges of CLK
e
e
e
0 during programming WAIT will remain negated during burst portion of access
0 during programming WAIT will remain high during non-delayed accesses WAIT
1 during programming DTACK will be asserted when RAS is asserted
e
e
e
e
e
2 positive edges of CLK
3 positive edges of CLK
2 positive edges of CLK
4 positive edges of CLK
0 during programming WAIT will remain high during non-delayed accesses
(Continued)
12
Description