MM5452V/NOPB National Semiconductor, MM5452V/NOPB Datasheet - Page 4

• Manufacturer Part Number: MM5452V/NOPB
• Description: IC DVR LCD 32 SEG DISPLAY 44PLCC
• Manufacturer: National Semiconductor

Specifications of MM5452V/NOPB

• Display Type: LCD
• Configuration: 7 Segment + DP, Alphanumeric & Bar Graph
• Interface: Serial
• Digits Or Characters: 4.5 Digits
• Voltage - Supply: 3 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Operating Supply Voltage (typ): 3.3/5/9V
• Number Of Digits: 4.5
• Number Of Segments: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: PLCC
• Pin Count: 44
• Mounting: Surface Mount
• Power Dissipation: 350mW
• Frequency (max): 1MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant
• Other names: *MM5452V; *MM5452V/NOPB; MM5452V

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Functional Description
The MM5452 is specifically designed to operate 4½-digit 7-
segment displays with minimal interface with the display and
the data source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals, serial data
and clock. Since the MM5452 does not contain a character
generator, the formatting of the segment information must be
done prior to inputting the data to the MM5452. Using a format
of a leading “1” followed by the 32 data bits allows data trans-
fer without an additional load signal. The 32 data bits are
latched after the 36th clock is complete, thus providing non-
multiplexed, direct drive to the display. Outputs change only
if the serial data bits differ from the previous time.
A block diagram is shown in Figure 1. For the MM5452 a
DATA ENABLE is used instead of the 33rd output. If the DATA
ENABLE signal is not required, the 33rd output can be
brought out. This is the MM5453 device.
Figure 4 shows a typical application. Note how the input data
maps to the output pins and the display. The MM5452 and
MM5453 do not have format restrictions, as all outputs are
FIGURE 3. Input Data Format
FIGURE 2. Timing Diagram
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Figure 3 shows the input data format. A start bit of logical “1”
precedes the 32 bits of data. At the 36th clock a LOAD signal
is generated synchronously with the high state of the clock,
which loads the 32 bits of the shift registers into the latches.
At the low state of the clock a RESET signal is generated
which clears all the shift registers for the next set of data. The
shift registers are static master-slave configuration. There is
no clear for the master portion of the first shift register, thus
allowing continuous operation.
If the clock is not continuous, there must be at least a com-
plete set of 36 clocks otherwise the shift registers will not load
and clear.
Bit 1 is the first bit following the start bit and it will appear on
device pin 18 of the MM5452N and MM5453N, and on device
pin 20 of the MM5452V and MM5453V.
Figure 2 shows the timing relationships between data, clock
and DATA ENABLE.
controllable. The application assumes a specific display
pinout. Different display/driver connection patterns will, of
course, yield a different input data format.
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