LTC4211IS8 Linear Technology, LTC4211IS8 Datasheet - Page 15

• Manufacturer Part Number: LTC4211IS8
• Description: IC CTRLR HOTSWAP CURR CTRL 8SOIC
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4211IS8

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.5 V ~ 16.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass
transistor is pulled to ground by the internal 200µA current
source connected at the GATE pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4211 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10µA current source.
Once V
LTC4211 checks to make sure that GATE is OFF (V
0.2V) at Time Point 2. An internal timing circuit is enabled
and the TIMER pin voltage ramps up at the rate described
by Equation 1. At Time Point 3 (the timing period pro-
grammed by C
(1.236V). Next, the TIMER pin voltage ramps down to
Time Point 4 where the LTC4211 performs two checks: (1)
FILTER pin voltage is low (V
FAULT pin voltage is high (V
conditions are met, the LTC4211 begins a second timing
(soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point 5),
the LTC4211’s FAST COMP is armed and an internal 10µA
current source working with an internal charge pump
provides the gate drive to the external pass transistor. An
expression for the GATE voltage slew rate is given by
Equation 3:
where C
(C
For example, a Si4410DY (a 30V N-channel power MOSFET)
exhibits an approximate C
LTC4211’s GATE voltage rate-of-change (slew rate) for
this example would be:
ISS
V
V
GATE
GATE
).
CC
GATE
Slew Rate
Slew Rate
and ON (the ON pin is >1.316) are valid, the
= Power MOSFET gate input capacitance
TIMER
U
), the TIMER pin voltage equals V
,
,
dV
dV
GATE
GATE
dt
dt
GATE
=
=
of 3300pF at V
FILTER
FAULT
3300
C
10
10
GATE
µ
µ
A
> 1.286V). If both
A
pF
< 1.156V) and (2)
=
3 03
GS
.
= 10V. The
ms
V
GATE
TMR
(3)
<
The inrush current being delivered to the load while the
GATE is ramping is dependent on C
Equation 4 gives an expression for the inrush current
during the second timing cycle:
For example, if C
inrush current charging C
At Time Point 6, the output voltage trips COMP2’s thresh-
old, signaling an output voltage “power good” condition.
At Time Point 7, RESET is asserted high, SLOW COMP is
armed and the LTC4211 enters a fault monitor mode. The
TIMER voltage then ramps down to Time Point 8.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
voltage is ramped to ground by the internal 200µA current
source, discharging C
sistor. As C
COMP2’s threshold, signaling a “power bad” condition at
Time Point 10. At this point, RESET is asserted low.
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current was
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to C
inrush current is large enough to cause a voltage drop
greater than 50mV across the sense resistor, an internal
servo loop controls the operation of the 10µA current
source at the GATE pin to regulate the load current to:
For example, the inrush current is limited to 5A when
R
SENSE
I
I
I
INRUSH
INRUSH
LIMIT SOFTSTART
= 0.01Ω.
(
=
=
LOAD
10
dV
µ
GATE
dt
GATE
A
discharges, the output voltage crosses
•
)
0 0033
=
•
= 3300pF and C
2000
GATE
.
C
R
50
LOAD
SENSE
LOAD
mV
and turning off the pass tran-
µ
µ
ON
F
F
=
is:
< 1.236V). The GATE pin
=
10
6 06
µ
.
A
LOAD
•
A
LOAD
C
C
LTC4211
LOAD
GATE
= 2000µF, the
LOAD
and C
15
. If the
GATE
4211fa
(4)
(5)
(6)
.