LTC4211IS8 Linear Technology, LTC4211IS8 Datasheet - Page 17

• Manufacturer Part Number: LTC4211IS8
• Description: IC CTRLR HOTSWAP CURR CTRL 8SOIC
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4211IS8

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.5 V ~ 16.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
or by actively limiting the inrush current. The LTC4211
uses GATE voltage slew rate limiting when C
and/or the inrush current limit is set high. If GATE voltage
slew rate control is preferred with large C
capacitor (C
shown in Figure 7. According to Equation 3, adding C
slows the GATE voltage slew rate at the expense of slower
system turn-on and turn-off time. Should this technique
be used, values for C
An external gate capacitor may also be useful to decrease
or eliminate current spikes through the MOSFET when
power is first applied. At power-up, the instantaneous in-
put voltage step attempts to pull the MOSFET gate up
through the MOSFET’s drain-to-gate capacitance. If the
MOSFET’s C
enough to turn on the MOSFET, thereby allowing a current
spike to the output. This event occurs during the time that
the LTC4211 is coming out of UVLO and getting its intel-
ligence to hold the GATE pin low. An external capacitor
attenuates the voltage to which the GATE is pulled up and
eliminates the current spike. The value required is depen-
dent on the MOSFET capacitance specifications. In typical
applications, this capacitor is not required.
ELECTRONIC CIRCUIT BREAKER
The LTC4211 features an electronic circuit breaker func-
tion that protects against supply overvoltage, externally-
generated fault conditions and shorts or excessive load
current conditions on the supply. If the circuit breaker
V
5V
**
IN
*
VALUES ≤150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY
GATE Voltage Slew Rate Control and Large C
Figure 7. Using an External Capacitor at GATE for
V
CC
GX
R
0.007Ω
GS
SENSE
) can be used from GATE to ground, as
is small, the gate can be pulled up high
SENSE
LTC4211**
U
GX
less than 150nF are recommended.
Si4410DY
GATE
M1
FB
C
dV
V
GX
GATE
GATE
dt
*
SLEW RATE CONTROL
=
(
C
GATE
R1
36k
R2
15k
4211 F07
10µA
LOAD
+ C
+
GX
LOAD
, an external
)
LOAD
C
LOAD
is small
V
5V
5A
OUT
GX
trips, the GATE pin is immediately pulled to ground, the
external N-channel MOSFET is quickly turned OFF and
FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4211’s SLOW COMP and FAST COMP thresholds (see
Block Diagram). The SLOW COMP trips the circuit breaker
if the voltage across the SENSE resistor (V
V
cations where this comparator’s response time is not long
enough, for example, because of excessive supply voltage
noise. To adjust the response time of the SLOW COMP, the
MS version of the LTC4211 is chosen and a capacitor is
used at the LTC4211’s FILTER pin (see section on Adjust-
ing SLOW Comp’s Response Time). The FAST COMP trips
the circuit breaker to protect against fast load overcurrents
if the transient voltage across the sense resistor is greater
than 150mV for 300ns. The response time of the LTC4211’s
FAST COMP is fixed.
The timing diagram of Figure 6 illustrates when the
LTC4211’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4211’s FAST COMP is armed at
Time Point 5. Arming FAST COMP at Time Point 5 ensures
that the system is protected against a short-circuit
condition during the second timing cycle after C
been fully charged. At Time Point 7, SLOW COMP is
armed when the internal control loop is disengaged.
The timing diagrams in Figures 8 and 9 illustrate the opera-
tion of the LTC4211 when the load current conditions exceed
the thresholds of the FAST COMP (V
and SLOW COMP (V
RESETTING THE ELECTRONIC CIRCUIT BREAKER
Once the LTC4211’s circuit breaker is tripped, FAULT is
asserted low and the GATE pin is pulled to ground. The
LTC4211 remains latched OFF in this fault state until the
external fault is cleared. To clear the internal fault detect
circuitry and to restart the LTC4211, its ON pin must be
driven low (V
time FAULT goes high. Toggling the ON pin from low to
high (V
LTC4211. The timing diagram in Figure 10 illustrates a
CB
) is greater than 50mV for 20µs. There may be appli-
ON
> 1.316V) initiates a restart sequence in the
ON
< 1.236V) for at least 150µs, after which
CB(SLOW)
> 50mV), respectively.
CB(FAST)
LTC4211
CC
– V
> 150mV)
LOAD
SENSE
17
4211fa
has
=