LM3431QMH/NOPB National Semiconductor, LM3431QMH/NOPB Datasheet - Page 22

• Manufacturer Part Number: LM3431QMH/NOPB
• Description: IC LED DRVR HP CONS CURR 28TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: High Power, Constant Currentr

Specifications of LM3431QMH/NOPB

• Constant Current: Yes
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 3
• Internal Driver: No
• Type - Primary: Automotive
• Type - Secondary: High Brightness LED (HBLED)
• Frequency: 651kHz ~ 1.1MHz
• Voltage - Supply: 4.5 V ~ 36 V
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 200mA
• Internal Switch(s): Yes
• Efficiency: 88%
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Number Of Segments: 6
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Package Type: TSSOP EP
• Pin Count: 28
• Mounting: Surface Mount
• Power Dissipation: 3.1W
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 36V
• Led Driver Application: Display Backlighting, Automotive Lighting
• No. Of Outputs: 3
• Output Current: 200mA
• Output Voltage: 40V
• Input Voltage: 5V To 37V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Compliant
• Other names: LM3431QMH

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The current sensing circuitry in current mode controllers can
be easily affected by switching noise. Although the LM3431
imposes 170ns of blanking time at the beginning of every cy-
cle to ignore this noise, some may remain after the blanking
time. Following the important guidelines below will help min-
imize switching noise and its effect on current sensing.
As shown in Figure 15, ground the output capacitor as close
as possible to the bottom of the sense resistor. This connec-
tion should be somewhat isolated from the rest of the PGND
plane (place no ground plane vias in this area). The V
of the output capacitor should be placed close to the diode.
The SW node (the node connecting the diode anode, induc-
tor, and FET drain) should be kept as small as possible. This
node is one of the main sources for radiated EMI. Sensitive
traces should not be routed in the area of the SW node or
inductor.
The CS pin is sensitive to noise. Be sure to route this trace
away from the inductor and the switch node. The CS, LG, and
ILIM traces should be kept as short as possible. As shown
below, R4 must be grounded close to the ground side of R3.
The VCC capacitor should be placed as close as possible to
the IC and grounded close to the PGND pin. Take care in
routing any other VCC traces away from noise sources and
use decoupling capacitors when using VCC as an external
voltage supply.
A ceramic input capacitor must be connected as close as
possible to the VIN pin and grounded close to the PGND pin.
An isolated ground area shown as SGND is recommended
for small signal ground connections. The SGND plane should
connect to both the exposed pad (EP) and SGND pin. The
SGND and PGND ground planes should be connected to their
respective pins and both pins should be connected only
through the exposed pad, EP.
Components connecting all of the following pins should be
placed close to the device and grounded to the SGND plane:
REF, REFIN, AFB, COMP, RT, FF, MODE/F, and SS/SH.
These components and their traces should not be routed near
the switch node or inductor. The LED current sense resistors
OUT
side
22
should be grounded to the SGND plane for accurate current
sensing. This area, shown as LGND in Figure 15, should be
somewhat separated from SGND and must provide enough
copper area for the total LED current.
If driving more than 3 channels, the layout of the additional
channels should be within a minimal area with short trace
lengths. This will help to reduce ringing and delay times. Con-
nections to the LED array should be as short as possible. Less
than 25 cm is recommended. Longer lead lengths can cause
excessive ringing or oscillation.
A large, continuous ground plane should be placed as an in-
ner or bottom layer for thermal dissipation. This plane should
be considered as a PGND area and not used for SGND con-
nections. To optimize thermal performance, multiple vias
should be placed directly below the exposed pad to increase
heat flow into the ground plane. The recommended number
of vias is 10-12 with a hole diameter between 0.20 mm and
0.33 mm. See Application Note AN-1520 for more informa-
tion.
FIGURE 15. Example PCB Layout
30041161