MC33151PG ON Semiconductor, MC33151PG Datasheet - Page 6

• Manufacturer Part Number: MC33151PG
• Description: IC MOSFET DRIVER DUAL HS 8-DIP
• Manufacturer: ON Semiconductor
• Type: High Speedr

Specifications of MC33151PG

• Configuration: Low-Side
• Input Type: Inverting
• Delay Time: 35ns
• Current - Peak: 1.5A
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 6.5 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Rise Time: 31 ns
• Fall Time: 32 ns
• Supply Voltage (min): 6.5 V
• Supply Current: 10.5 mA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Driver Configuration: Inverting
• Driver Type: High Speed
• Input Logic Level: CMOS/LSTTL
• Propagation Delay Time: 100ns
• Operating Supply Voltage (max): 18V
• Peak Output Current: 1.5A
• Power Dissipation: 1W
• Operating Supply Voltage (min): 6.5V
• Operating Supply Voltage (typ): 12V
• Turn Off Delay Time: 100fs
• Turn On Delay Time (max): 100ps
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC33151PG; MC33151PGOS

Description
specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.
Input Stage
threshold centered at 1.67 V. The input thresholds are
insensitive to V
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to V
the output of one channel to directly drive the input of a
second channel for master−slave operation. Each input has
a 30 kW pulldown resistor so that an unconnected open input
will cause the associated Drive Output to be in a known high
state.
The MC34151 is a dual inverting high speed driver
The Logic Inputs have 170 mV of hysteresis with the input
80
60
40
20
80
60
40
20
Figure 16. Supply Current versus Input Frequency
0
0
0.1
10 k
Both Logic Inputs Driven
Both Drive Outputs Loaded
T
1 - V
2 - V
3 - V
4 - V
Figure 14. Drive Output Rise and Fall Time
V
V
T
A
50% Duty Cycle
A
0 V to 5.0 V,
CC
IN
= 25°C
= 25°C
= 0 V to 5.0 V
CC
CC
CC
CC
= 12 V
= 18 V, C
= 12 V, C
= 18 V, C
= 12 V, C
CC
C
versus Load Capacitance
L
, OUTPUT LOAD CAPACITANCE (nF)
making this device directly compatible
L
L
L
L
f, INPUT FREQUENCY (Hz)
= 2.5 nF
= 2.5 nF
= 1.0 nF
= 1.0 nF
1.0
100
t
f
t
r
1
CC
APPLICATIONS INFORMATION
2
. This allows
3
4
http://onsemi.com
1.0 M
10
6
Output Stage
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 W at
1.0 A. The low ‘on’ resistance allows high output currents
to be attained at a lower V
drivers. Each output has a 100 kW pulldown resistor to keep
the MOSFET gate low when V
current or thermal protection has been designed into the
device, so output shorting to V
avoided.
driver outputs to ring above V
transition, and below ground during the turn−off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34151 is
immune to output latchup. The Drive Outputs contain an
internal diode to V
transients. When operating with V
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across
Each totem pole Drive Output is capable of sourcing and
Parasitic inductance in series with the load will cause the
8.0
6.0
4.0
2.0
80
60
40
20
0
0
Figure 17. Supply Current versus Supply Voltage
0.1
Figure 15. Supply Current versus Drive Output
0
V
Both Logic Inputs Driven
Both Drive Outputs Loaded
T
T
A
CC
A
0 V to 5.0 V
50% Duty Cycle
= 25°C
= 25°C
= 12 V
C
L
4.0
, OUTPUT LOAD CAPACITANCE (nF)
Load Capacitance
Low State Drive Outputs
V
CC
CC
Logic Inputs at V
, SUPPLY VOLTAGE (V)
f = 500 kHz
CC
for clamping positive voltage
than with comparative CMOS
8.0
1.0
CC
is less than 1.4 V. No over
CC
CC
CC
CC
at 18 V, proper power
High State Drive Outputs
or ground must be
during the turn−on
Logic Inputs Grounded
f = 200 kHz
f = 50 kHz
12
10
16