MC33926PNBR2 Freescale Semiconductor, MC33926PNBR2 Datasheet - Page 12

• Manufacturer Part Number: MC33926PNBR2
• Description: IC H-BRIDGE THROTTLE CTRL 32-QFN
• Manufacturer: Freescale Semiconductor
• Type: H Bridger

Specifications of MC33926PNBR2

• Input Type: Non-Inverting
• Number Of Outputs: 2
• On-state Resistance: 120 mOhm
• Current - Output / Channel: 5A
• Current - Peak Output: 11A
• Voltage - Supply: 5 V ~ 28 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Product: H-Bridge Drivers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

torque, direction, dynamic breaking, PWM control, and
closed-loop control) make the 33926 a very attractive, cost-
effective solution for controlling a broad range of small DC
motors. The 33926 outputs are capable of supporting peak
DC load currents of up to 5.0 A from a 28 V
internal charge pump and gate drive circuitry are provided
that can support external PWM frequencies up to 20 kHz.
pin (the FB pin) that provides a constant-current source
ratioed to the active high side
used to provide “real time” monitoring of output current to
facilitate closed-loop operation for motor speed/torque
control, or for the detection of open load conditions.
the two totem-pole half-bridge outputs. An input invert, INV,
changes IN1 and IN2 to LOW = true logic. Two different
output slew rates are selectable via the SLEW input. Two
independent disable inputs, D1 and
force the H-Bridge outputs to a high-impedance state (all H-
Bridge switches OFF). An EN pin controls an enable function
POWER GROUND AND ANALOG GROUND
(PGND AND AGND)
together with a very low-impedance connection.
POSITIVE POWER SUPPLY (VPWR)
VPWR pins must be connected together on the printed circuit
board with as short as possible traces, offering as low-
impedance as possible between pins.
Threshold will result in the protection activating. It is essential
to use an input filter capacitor of sufficient size and low ESR
to sustain a V
switched (See
18).
STATUS FLAG (SF)
active LOW open drain structure requiring a pull-up resistor
to V
Table, page
INPUT INVERT (INV)
TRUE. This is a Schmitt trigger input with
default condition is non-inverted. If IN1 and IN2 are set so
12
33926
FUNCTIONAL DESCRIPTION
INTRODUCTION
Numerous protection and operational features (speed,
The 33926 has an analog feedback (current mirror) output
Two independent inputs, IN1 and IN2, provide control of
The power and analog ground pins should be connected
VPWR pins are the power supply inputs to the device. All
Transients on V
This pin is the device fault status output. This output is an
The Input Invert Control pin sets IN1 and IN2 to LOW =
DD
. The maximum V
16
PWR
33926 Typical Application Schematic on page
for the SF Output status definition.
PWR
greater than V
which go below the Under-voltage
DD
is < 7.0 V. Refer to
MOSFETs’
UVLO
D2
, provide the means to
when the load is
current. This can be
~ 80 µA
FUNCTIONAL DESCRIPTION
PWR
FUNCTIONAL PIN DESCRIPTION
Table 5, Truth
source. An
sink; the
INTRODUCTION
that allows the IC to be placed in a power-conserving Sleep
mode.
OFF-Time PWM Current Regulation), Output Short-circuit
Detection with Latch-OFF, and Over-temperature Detection
with Latch-OFF. Once the device is latched-OFF due to a
fault condition, either of the Disable inputs (D1 or D2), V
or EN must be “toggled” to clear the status flag.
accomplished by a constant-OFF time PWM method using
current limit threshold triggering. The current limiting scheme
is unique in that it incorporates a junction temperature-
dependent current limit threshold. This means that the
current limit threshold is “reduced to around 4.2 A” as the
junction temperature increases above 160°C. When the
temperature is above 175°C, over-temperature shutdown
(latch-OFF) will occur. This combination of features allows
the device to continue operating for short periods of time (< 30
seconds) with unexpected loads, while still retaining
adequate protection for both the device and the load.
that the current is being commanded to flow through the load
attached between OUT1 and OUT2, changing the logic level
at INV will have the effect of reversing the direction of current
commanded. Thus, the INV input may be used as a “forward/
reverse” command input. If both IN1 and IN2 are the same
logic level, then changing the logic level at INV will have the
effect of changing the bridge’s output from freewheeling high
to freewheeling low or vice versa.
SLEW RATE (SLEW)
slew rate. Schmitt trigger input with ~ 80 µA sink so the
default condition is SLOW. When SLEW is set to SLOW,
PWM-ing should be limited to frequencies less than 11 kHz in
order to allow the internal high-side driver circuitry time to
fully enhance the high-side MOSFETs.
INPUT 1,2 AND DISABLE INPUT 1,2
(IN1, IN2, AND D1, D2
outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible
inputs with hysteresis. IN1 and IN2 independently control
OUT1 and OUT2, respectively. D1 and
complementary inputs used to tri-state disable the H-Bridge
outputs.
D2
OUT2 are both tri-state disabled; however, the rest of the
The 33926 has Output Current Limiting (via Constant
Current limiting (Load Current Regulation) is
The SLEW pin is the logic input that selects fast or slow
These pins are input control pins used to control the
When either D1 or
= logic LOW) in the disable state, outputs OUT1 and
D2
Analog Integrated Circuit Device Data
is SET (D1 = logic HIGH or
)
Freescale Semiconductor
D2
are
PWR
,