MC33886DHR2 Freescale Semiconductor, MC33886DHR2 Datasheet - Page 7

• Manufacturer Part Number: MC33886DHR2
• Description: IC H-BRIDGE 5.0A 20-HSOP
• Manufacturer: Freescale Semiconductor

Specifications of MC33886DHR2

• Applications: DC Motor Controller, H Bridge
• Number Of Outputs: 1
• Current - Output: 5A
• Voltage - Supply: 5 V ~ 40 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-HSOP
• For Use With: KIT33886DHEVB - KIT EVAL FOR MC33886 H-BRIDGE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -

Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V
reflect the approximate parameter mean at T
TIMING CHARACTERISTICS
Notes
PWM Frequency
Maximum Switching Frequency During Active Current Limiting
Output ON Delay
Output OFF Delay
Output Rise and Fall Time
Output Latch-OFF Time
Output Blanking Time
Output FET Body Diode Reverse Recovery Time
Disable Delay Time
Short Circuit / Overtemperature Turn-
Power-OFF Delay Time
21.
22.
23.
24.
25.
26.
27.
V+ = 14 V
V+ = 14 V
V+ = 14 V, I
The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM
pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. Refer to Typical Switching Waveforms,
The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant
OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.
Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to
the 10% point of the output response signal. See
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See
Parameter is guaranteed by design but not production tested.
Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure
Increasing currents will become limited at I
state latch-OFF. See
above 160
latch-OFF will occur. See
5, page 8.
OUT
°
(21)
(23)
C will cause the active current limiting to progressively “fold-back” (or decrease) to 2.5 A typical at 175
(23)
= 3.0 A
(26)
(24)
Figures 8
Characteristic
Figure
OFF
and 9, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature
7, page 8.
DYNAMIC ELECTRICAL CHARACTERISTICS
Time
(27)
LIM
≤
A
(25)
V+
= 25°C under nominal conditions unless otherwise noted.
. Hard shorts will breach the I
≤
Figure
28 V and -40°C
Figures 10
(22)
4, page 8.
through 17, pp. 10–11.
≤
T
A
t
Symbol
≤
d (disable)
t
t
t
f
f
d (OFF)
FAULT
d
t
t
PWM
125°C unless otherwise noted. Typical values noted
MAX
SCH
f
(ON)
t
pod
t
t
, t
r r
a
b
r
or I
SCL
DYNAMIC ELECTRICAL CHARACTERISTICS
limit, forcing the output into an immediate tri-
Min
100
2.0
15
12
–
–
–
–
–
–
–
ELECTRICAL CHARACTERISTICS
20.5
16.5
Typ
5.0
4.0
1.0
–
–
–
–
–
–
°
C where thermal
Max
Figure
8.0
8.0
5.0
10
20
18
18
26
21
–
–
6, page 8.
Unit
kHz
kHz
ms
µs
µs
µs
µs
µs
ns
µs
µs
33886
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