MC34929EPR2 Freescale Semiconductor, MC34929EPR2 Datasheet - Page 14

• Manufacturer Part Number: MC34929EPR2
• Description: IC MOTOR DRIVER BLDC 1A 24-QFN
• Manufacturer: Freescale Semiconductor
• Type: Brushless DC Motor Controllerr

Specifications of MC34929EPR2

• Applications: DC Motor Driver, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Current - Output: 1A
• Voltage - Supply: 8 V ~ 28 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Operating Current: 6mA
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 8V
• Operating Supply Voltage (typ): 12V
• Operating Supply Voltage (max): 28V
• Operating Supply Voltage: 12 V
• Supply Current: 6 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Compliant

the 34929 as shown in
CHARGE PUMP
supply for the high side power MOSFET gate drive. Its output
voltage is limited to V+ +10V to prevent damage to the driver
circuits or MOSFET gates. However, VGHS will be below V+
+10V if V+ supply voltage is below 12V. The switching
frequency of this charge pump is ~250 kHz. The VGHS
supply wakes up typically 1ms after the RUN command is
initiated.
REGULATORS AND VOLTAGE REFERENCE
voltages for use by the analog/mixed-signal circuitry. This
function also includes providing the drive voltage for the low-
side gate drivers. The regulators for the internal logic and
analog circuits comprise regulators for the logic circuits, and
regulators for the analog circuits (including input/output
buffering, but excepting the power outputs). A bandgap
circuit generates the internal precision reference voltage
(1.25 V). This is used for biasing the comparators and other
analog circuits. (Note: this reference voltage is not externally
available.)
INTERNAL CLOCK
the IC’s logic circuits. Its output frequency is 1.0 MHz ±30%.
The clock circuit also includes frequency-dividers to derive
lower frequency pulse trains for use by circuits such as the
charge pump and various internal timers, etc.).
INPUT LOGIC
connected to the internal Vdd logic supply. The logic input
circuitry includes the following inputs:
• PWM input controls the speed of motor. Output = “Enable”
• RUN input controls the start and stop function. When RUN
• DIR input controls the direction of motor. When DIR is
14
34929
FUNCTIONAL DEVICE OPERATION
The following paragraphs describe the internal function of
This charge pump provides the VGHS and internal power
Internal regulators provide operating and reference
The internal clock generates a stable pulse-train for use by
All logic input pins have internal 100K
when PWM = “L”, and then Output = “Disable” (means “Z”:
High Impedance) when PWM = “H”.
= “H”, this IC will go to suspend mode via controlled brake
state and suspend unnecessary circuits (Internal OSC,
Counters, Charge pump, Stall detection and protection).
flipped, the motor will be reverse, brake through controlled
brake, and then rotate to reverse direction. This DIR pin
has capability to be applied to V+ + VF.
Figure
2.
FUNCTIONAL DEVICE OPERATION
pull-ups
HALL COMPARATORS
sensors.
HALL SWITCH
current.
TACH, 3XTACH OUTPUT
HAB signal. 3XTACH is from inverted EXOR with all three
Hall sensor signals. These outputs are both open drain type.
LOW V+ DETECT
voltage falls below the threshold, the IC will reset after
T
transients on V+ within the
suspend mode, V+ must return to a level greater than the
detection threshold plus and additional 100mv (typical)
hysteresis, and stay there for the
will come out of suspend mode.
RESET
condition, such as V+ falling below the
detected, the IC will be in placed in suspend mode (all output
MOSFETs set to a high impedance state) by way of a
controlled-braking transition state. This will occur regardless
of RUN command status. Note, the error condition must exist
for a time period greater than
will be generated. When the error condition resolves,
suspend mode will be released after the
Figure
STALL DETECTION AND PROTECTION
operation for a stalled rotor event while the RUN command is
set = “True”. A stall is detected as follows (see
TC, is monitored by the stall-detect counter which is counting
the sawtooth cycles.
time there is a transition on any of the outputs from the Hall
comparators (HAB, HBC, or HCA).
counter is allowed to overflow, (i.e., anytime the counter is not
cleared back to zero by the EXOR’ed output of the HAB,
HBC, and HCA comparators). This can only occur when at
least two of the signals (HAB, HBC, or HCA) have become
static (fixed to “H” or “L”).
SPND
The Hall comparators square-up the signals from the Hall
A high side switch to turn-on and turn-off the Hall supply
The TACH outputs are as follows: TACH is the inverted
The low V+ voltage detection circuit monitors V+; if the V+
The reset function works as follows: when an error
The stall detection and protection circuit actively monitors
1) A sawtooth waveform generated at the timing capacitor,
2) The stall-detect counter is being reset (cleared) every
3) A “stall condition” is assumed anytime the stall-detect
time. This circuitry will not respond to negative-going
6.)
Analog Integrated Circuit Device Data
T
SPND
T
SPND
time period. Once placed in
T
WAIT
Freescale Semiconductor
before the internal reset
period, before the IC
V+
T
-LV
WAIT
threshold, is
period. (See
Figure
7):